yannick.naumann/RT-Task-Generator-QEMU
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RT-Task-Generator-QEMU/target/riscv/insn_trans
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LIU Zhiwei d8c40c24fd target/riscv: Adjust scalar reg in vector with XLEN 
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21 15:52:57 +10:00
..
trans_privileged.c.inc
target/riscv: Sign extend pc for different XLEN
2022-01-21 15:52:57 +10:00
trans_rva.c.inc
target/riscv: Calculate address according to XLEN
2022-01-21 15:52:57 +10:00
trans_rvb.c.inc
target/riscv: support for 128-bit arithmetic instructions
2022-01-08 15:46:10 +10:00
trans_rvd.c.inc
target/riscv: Calculate address according to XLEN
2022-01-21 15:52:57 +10:00
trans_rvf.c.inc
target/riscv: Calculate address according to XLEN
2022-01-21 15:52:57 +10:00
trans_rvh.c.inc
exec/memop: Adding signedness to quad definitions
2022-01-08 15:46:10 +10:00
trans_rvi.c.inc
target/riscv: Calculate address according to XLEN
2022-01-21 15:52:57 +10:00
trans_rvm.c.inc
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
trans_rvv.c.inc
target/riscv: Adjust scalar reg in vector with XLEN
2022-01-21 15:52:57 +10:00
trans_rvzfh.c.inc
target/riscv: zfh: implement zfhmin extension
2021-12-20 14:51:36 +10:00