yannick.naumann/RT-Task-Generator-QEMU
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RT-Task-Generator-QEMU/target/riscv
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LIU Zhiwei f297245f6a target/riscv: Relax UXL field for debugging 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21 15:52:57 +10:00
..
insn_trans
target/riscv: Adjust scalar reg in vector with XLEN
2022-01-21 15:52:57 +10:00
arch_dump.c
target-riscv: support QMP dump-guest-memory
2021-03-04 09:43:29 -05:00
bitmanip_helper.c
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
cpu_bits.h
target/riscv: Enable uxl field write
2022-01-21 15:52:57 +10:00
cpu_helper.c
target/riscv: Split out the vill from vtype
2022-01-21 15:52:57 +10:00
cpu_user.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
cpu-param.h
target/riscv: Add a virtualised MMU Mode
2020-11-09 15:08:45 -08:00
cpu.c
target/riscv: Set default XLEN for hypervisor
2022-01-21 15:52:57 +10:00
cpu.h
target/riscv: Remove VILL field in VTYPE
2022-01-21 15:52:57 +10:00
csr.c
target/riscv: Relax UXL field for debugging
2022-01-21 15:52:57 +10:00
fpu_helper.c
target/riscv: add "set round to odd" rounding mode helper function
2021-12-20 14:53:31 +10:00
gdbstub.c
target/riscv: Use gdb xml according to max mxlen
2022-01-21 15:52:57 +10:00
helper.h
target/riscv: Don't save pc when exception return
2022-01-21 15:52:57 +10:00
insn16.decode
target/riscv: accessors to registers upper part and 128-bit load/store
2022-01-08 15:46:10 +10:00
insn32.decode
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
instmap.h
target/riscv: progressively load the instruction during decode
2020-02-25 20:20:23 +00:00
internals.h
target/riscv: add "set round to odd" rounding mode helper function
2021-12-20 14:53:31 +10:00
Kconfig
meson: Introduce target-specific Kconfig
2021-07-09 18:21:34 +02:00
kvm_riscv.h
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm-stub.c
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm.c
target/riscv: Implement virtual time adjusting with vm state changing
2022-01-21 15:52:56 +10:00
m128_helper.c
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
machine.c
target/riscv: Split out the vill from vtype
2022-01-21 15:52:57 +10:00
meson.build
target/riscv: Support start kernel directly by KVM
2022-01-21 15:52:56 +10:00
monitor.c
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-22 07:47:51 +10:00
op_helper.c
target/riscv: Adjust csr write mask with XLEN
2022-01-21 15:52:57 +10:00
pmp.c
target/riscv: Adjust pmpcfg access with mxl
2022-01-21 15:52:57 +10:00
pmp.h
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
sbi_ecall_interface.h
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
2022-01-21 15:52:56 +10:00
trace-events
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate.c
target/riscv: Split pm_enabled into mask and base
2022-01-21 15:52:57 +10:00
vector_helper.c
target/riscv: Adjust vector address with mask
2022-01-21 15:52:57 +10:00