189 lines
4.7 KiB
Plaintext
189 lines
4.7 KiB
Plaintext
/*
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* P1022 RDK 32-bit Physical Address Map Device Tree Source
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "p1022si-pre.dtsi"
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/ {
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model = "fsl,P1022RDK";
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compatible = "fsl,P1022RDK";
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memory {
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device_type = "memory";
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};
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board_lbc: lbc: localbus@ffe05000 {
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/* The P1022 RDK does not have any localbus devices */
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status = "disabled";
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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i2c@3100 {
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wm8960:codec@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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/* MCLK source is a stand-alone oscillator */
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clock-frequency = <12288000>;
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};
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rtc@68 {
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compatible = "st,m41t62";
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reg = <0x68>;
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};
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adt7461@4c{
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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zl6100@21{
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compatible = "isil,zl6100";
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reg = <0x21>;
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};
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zl6100@24{
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compatible = "isil,zl6100";
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reg = <0x24>;
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};
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zl6100@26{
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compatible = "isil,zl6100";
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reg = <0x26>;
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};
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zl6100@29{
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compatible = "isil,zl6100";
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reg = <0x29>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,m25p80", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <1000000>;
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partition@0 {
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label = "full-spi-flash";
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reg = <0x00000000 0x00100000>;
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};
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};
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};
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ssi@15000 {
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fsl,mode = "i2s-slave";
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codec-handle = <&wm8960>;
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};
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usb@22000 {
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phy_type = "ulpi";
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};
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usb@23000 {
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phy_type = "ulpi";
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupts = <3 1 0 0>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <9 1 0 0>;
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reg = <0x2>;
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};
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};
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mdio@25000 {
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@b1000 {
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phy-handle = <&phy1>;
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tbi-handle = <&tbi0>;
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phy-connection-type = "sgmii";
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};
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};
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pci0: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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reg = <0x0 0xffe09000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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reg = <0 0xffe0a000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci2: pcie@ffe0b000 {
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ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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reg = <0 0xffe0b000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/include/ "p1022si-post.dtsi"
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