110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Unisoc Inc.
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*/
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#ifndef __SPRD_DPU_H__
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#define __SPRD_DPU_H__
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <video/videomode.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_print.h>
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#include <drm/drm_vblank.h>
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#include <uapi/drm/drm_mode.h>
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/* DPU Layer registers offset */
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#define DPU_LAY_REG_OFFSET 0x30
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enum {
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SPRD_DPU_IF_DPI,
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SPRD_DPU_IF_EDPI,
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SPRD_DPU_IF_LIMIT
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};
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/**
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* Sprd DPU context structure
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*
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* @base: DPU controller base address
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* @irq: IRQ number to install the handler for
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* @if_type: The type of DPI interface, default is DPI mode.
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* @vm: videomode structure to use for DPU and DPI initialization
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* @stopped: indicates whether DPU are stopped
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* @wait_queue: wait queue, used to wait for DPU shadow register update done and
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* DPU stop register done interrupt signal.
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* @evt_update: wait queue condition for DPU shadow register
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* @evt_stop: wait queue condition for DPU stop register
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*/
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struct dpu_context {
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void __iomem *base;
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int irq;
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u8 if_type;
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struct videomode vm;
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bool stopped;
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wait_queue_head_t wait_queue;
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bool evt_update;
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bool evt_stop;
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};
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/**
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* Sprd DPU device structure
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*
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* @crtc: crtc object
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* @drm: A point to drm device
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* @ctx: DPU's implementation specific context object
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*/
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struct sprd_dpu {
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struct drm_crtc base;
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struct drm_device *drm;
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struct dpu_context ctx;
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};
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static inline struct sprd_dpu *to_sprd_crtc(struct drm_crtc *crtc)
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{
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return container_of(crtc, struct sprd_dpu, base);
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}
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static inline void
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dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits)
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{
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u32 bits = readl_relaxed(ctx->base + offset);
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writel(bits | set_bits, ctx->base + offset);
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}
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static inline void
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dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits)
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{
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u32 bits = readl_relaxed(ctx->base + offset);
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writel(bits & ~clr_bits, ctx->base + offset);
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}
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static inline u32
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layer_reg_rd(struct dpu_context *ctx, u32 offset, int index)
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{
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u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;
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return readl(ctx->base + layer_offset);
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}
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static inline void
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layer_reg_wr(struct dpu_context *ctx, u32 offset, u32 cfg_bits, int index)
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{
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u32 layer_offset = offset + index * DPU_LAY_REG_OFFSET;
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writel(cfg_bits, ctx->base + layer_offset);
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}
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void sprd_dpu_run(struct sprd_dpu *dpu);
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void sprd_dpu_stop(struct sprd_dpu *dpu);
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#endif
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