llvm-for-llvmta/test/CodeGen/ARM/load_store_opt_kill.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s
---
name: f
# Make sure the load into $r0 doesn't clobber the base register before the second load uses it.
body: |
bb.0:
liveins: $r0, $r3
; CHECK-LABEL: name: f
; CHECK: $r3 = LDRi12 $r0, 12, 14 /* CC::al */, $noreg
; CHECK: $r0 = LDRi12 $r0, 8, 14 /* CC::al */, $noreg
$r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg
...