136 lines
5.2 KiB
YAML
136 lines
5.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s --check-prefix=SI
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s --check-prefix=VI
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---
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name: test_zextload_flat_i32_i8
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_zextload_flat_i32_i8
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; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
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; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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; VI-LABEL: name: test_zextload_flat_i32_i8
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; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; VI: $vgpr0 = COPY [[AND]](s32)
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%0:_(p0) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
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$vgpr0 = COPY %1
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...
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---
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name: test_zextload_flat_i32_i16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_zextload_flat_i32_i16
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; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
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; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
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; VI-LABEL: name: test_zextload_flat_i32_i16
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; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; VI: $vgpr0 = COPY [[AND]](s32)
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%0:_(p0) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
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$vgpr0 = COPY %1
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...
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---
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name: test_zextload_flat_i31_i8
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_zextload_flat_i31_i8
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; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
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; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
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; SI: $vgpr0 = COPY [[COPY1]](s32)
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; VI-LABEL: name: test_zextload_flat_i31_i8
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; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
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; VI: $vgpr0 = COPY [[COPY2]](s32)
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%0:_(p0) = COPY $vgpr0_vgpr1
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%1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
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%2:_(s32) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: test_zextload_flat_i64_i8
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_zextload_flat_i64_i8
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; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
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; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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; VI-LABEL: name: test_zextload_flat_i64_i8
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; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(p0) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_zextload_flat_i64_i16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_zextload_flat_i64_i16
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; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
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; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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; VI-LABEL: name: test_zextload_flat_i64_i16
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; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(p0) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_zextload_flat_i64_i32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_zextload_flat_i64_i32
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; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
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; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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; VI-LABEL: name: test_zextload_flat_i64_i32
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; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
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; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
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; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(p0) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 0)
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$vgpr0_vgpr1 = COPY %1
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...
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