98 lines
3.1 KiB
Plaintext
98 lines
3.1 KiB
Plaintext
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
|
|
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load-store exclusive
|
|
#------------------------------------------------------------------------------
|
|
|
|
#ldxp x14, x14, [sp]
|
|
0xee 0x3b 0x7f 0xc8
|
|
#CHECK: warning: potentially undefined instruction encoding
|
|
#CHECK-NEXT: 0xee 0x3b 0x7f 0xc8
|
|
|
|
#ldaxp w19, w19, [x1]
|
|
0x33 0xcc 0x7f 0x88
|
|
#CHECK: warning: potentially undefined instruction encoding
|
|
#CHECK-NEXT: 0x33 0xcc 0x7f 0x88
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load-store register (immediate post-indexed)
|
|
#------------------------------------------------------------------------------
|
|
|
|
0x63 0x44 0x40 0xf8
|
|
#CHECK: warning: potentially undefined instruction encoding
|
|
#CHECK-NEXT: 0x63 0x44 0x40 0xf8
|
|
|
|
0x42 0x14 0xc0 0x38
|
|
#CHECK: warning: potentially undefined instruction encoding
|
|
#CHECK-NEXT: 0x42 0x14 0xc0 0x38
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load-store register (immediate pre-indexed)
|
|
#------------------------------------------------------------------------------
|
|
|
|
0x63 0x4c 0x40 0xf8
|
|
#CHECK: warning: potentially undefined instruction encoding
|
|
#CHECK-NEXT: 0x63 0x4c 0x40 0xf8
|
|
|
|
0x42 0x1c 0xc0 0x38
|
|
#CHECK: warning: potentially undefined instruction encoding
|
|
#CHECK-NEXT: 0x42 0x1c 0xc0 0x38
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load-store register pair (offset)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# Unpredictable if Rt == Rt2 on a load.
|
|
|
|
0xe3 0x0f 0x40 0xa9
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0xe3 0x0f 0x40 0xa9
|
|
# CHECK-NEXT: ^
|
|
|
|
0xe2 0x8b 0x41 0x69
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0xe2 0x8b 0x41 0x69
|
|
# CHECK-NEXT: ^
|
|
|
|
0x82 0x88 0x40 0x2d
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0x82 0x88 0x40 0x2d
|
|
# CHECK-NEXT: ^
|
|
|
|
#------------------------------------------------------------------------------
|
|
# Load-store register pair (post-indexed)
|
|
#------------------------------------------------------------------------------
|
|
|
|
# Unpredictable if Rt == Rt2 on a load.
|
|
|
|
0xe3 0x0f 0xc0 0xa8
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0xe3 0x0f 0xc0 0xa8
|
|
# CHECK-NEXT: ^
|
|
|
|
0xe2 0x8b 0xc1 0x68
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0xe2 0x8b 0xc1 0x68
|
|
# CHECK-NEXT: ^
|
|
|
|
0x82 0x88 0xc0 0x2c
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0x82 0x88 0xc0 0x2c
|
|
# CHECK-NEXT: ^
|
|
|
|
# Also unpredictable if writeback clashes with either transfer register
|
|
|
|
0x63 0x94 0xc0 0xa8
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0x63 0x94 0xc0 0xa8
|
|
|
|
0x69 0x2d 0x81 0xa8
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0x69 0x2d 0x81 0xa8
|
|
|
|
0x29 0xad 0xc0 0x28
|
|
# CHECK: warning: potentially undefined instruction encoding
|
|
# CHECK-NEXT: 0x29 0xad 0xc0 0x28
|
|
|