98 lines
3.1 KiB
Plaintext
98 lines
3.1 KiB
Plaintext
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# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
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# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
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#------------------------------------------------------------------------------
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# Load-store exclusive
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#------------------------------------------------------------------------------
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#ldxp x14, x14, [sp]
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0xee 0x3b 0x7f 0xc8
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#CHECK: warning: potentially undefined instruction encoding
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#CHECK-NEXT: 0xee 0x3b 0x7f 0xc8
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#ldaxp w19, w19, [x1]
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0x33 0xcc 0x7f 0x88
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#CHECK: warning: potentially undefined instruction encoding
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#CHECK-NEXT: 0x33 0xcc 0x7f 0x88
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#------------------------------------------------------------------------------
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# Load-store register (immediate post-indexed)
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#------------------------------------------------------------------------------
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0x63 0x44 0x40 0xf8
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#CHECK: warning: potentially undefined instruction encoding
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#CHECK-NEXT: 0x63 0x44 0x40 0xf8
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0x42 0x14 0xc0 0x38
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#CHECK: warning: potentially undefined instruction encoding
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#CHECK-NEXT: 0x42 0x14 0xc0 0x38
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#------------------------------------------------------------------------------
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# Load-store register (immediate pre-indexed)
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#------------------------------------------------------------------------------
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0x63 0x4c 0x40 0xf8
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#CHECK: warning: potentially undefined instruction encoding
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#CHECK-NEXT: 0x63 0x4c 0x40 0xf8
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0x42 0x1c 0xc0 0x38
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#CHECK: warning: potentially undefined instruction encoding
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#CHECK-NEXT: 0x42 0x1c 0xc0 0x38
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#------------------------------------------------------------------------------
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# Load-store register pair (offset)
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#------------------------------------------------------------------------------
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# Unpredictable if Rt == Rt2 on a load.
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0xe3 0x0f 0x40 0xa9
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0xe3 0x0f 0x40 0xa9
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# CHECK-NEXT: ^
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0xe2 0x8b 0x41 0x69
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0xe2 0x8b 0x41 0x69
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# CHECK-NEXT: ^
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0x82 0x88 0x40 0x2d
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0x82 0x88 0x40 0x2d
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# CHECK-NEXT: ^
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#------------------------------------------------------------------------------
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# Load-store register pair (post-indexed)
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#------------------------------------------------------------------------------
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# Unpredictable if Rt == Rt2 on a load.
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0xe3 0x0f 0xc0 0xa8
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0xe3 0x0f 0xc0 0xa8
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# CHECK-NEXT: ^
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0xe2 0x8b 0xc1 0x68
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0xe2 0x8b 0xc1 0x68
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# CHECK-NEXT: ^
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0x82 0x88 0xc0 0x2c
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0x82 0x88 0xc0 0x2c
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# CHECK-NEXT: ^
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# Also unpredictable if writeback clashes with either transfer register
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0x63 0x94 0xc0 0xa8
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0x63 0x94 0xc0 0xa8
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0x69 0x2d 0x81 0xa8
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0x69 0x2d 0x81 0xa8
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0x29 0xad 0xc0 0x28
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: 0x29 0xad 0xc0 0x28
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