233 lines
6.7 KiB
LLVM
233 lines
6.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S -o - | FileCheck %s
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i7 @llvm.fshl.i7(i7, i7, i7)
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declare i7 @llvm.fshr.i7(i7, i7, i7)
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declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
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declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
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; extract(concat(0x12345678, 0xABCDEF01) << 5) = 0x468ACF15
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define i32 @fshl_i32() {
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; CHECK-LABEL: @fshl_i32(
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; CHECK-NEXT: ret i32 1183502101
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;
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%f = call i32 @llvm.fshl.i32(i32 305419896, i32 2882400001, i32 5)
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ret i32 %f
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}
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; extract(concat(0x12345678, 0xABCDEF01) >> 5) = 0xC55E6F78
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; Try an oversized shift to test modulo functionality.
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define i32 @fshr_i32() {
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; CHECK-LABEL: @fshr_i32(
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; CHECK-NEXT: ret i32 -983666824
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;
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%f = call i32 @llvm.fshr.i32(i32 305419896, i32 2882400001, i32 37)
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ret i32 %f
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}
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; Use a weird type.
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; Try an oversized shift to test modulo functionality.
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; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
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define i7 @fshl_i7() {
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; CHECK-LABEL: @fshl_i7(
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; CHECK-NEXT: ret i7 -61
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;
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%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 9)
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ret i7 %f
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}
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; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
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; Try an oversized shift to test modulo functionality.
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define i7 @fshr_i7() {
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; CHECK-LABEL: @fshr_i7(
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; CHECK-NEXT: ret i7 31
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;
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%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 16)
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ret i7 %f
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}
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; Vectors are folded by handling each scalar element individually, so this is the equivalent of 4 scalar tests:
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; extract(concat(0x00, 0xFF) << 0) = 0x00
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; extract(concat(0xFF, 0x00) << 0) = 0xFF
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; extract(concat(0x10, 0x55) << 1) = 0x20
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; extract(concat(0x11, 0xAA) << 2) = 0x46
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define <4 x i8> @fshl_v4i8() {
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; CHECK-LABEL: @fshl_v4i8(
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; CHECK-NEXT: ret <4 x i8> <i8 0, i8 -1, i8 32, i8 70>
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;
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%f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 0, i8 -1, i8 16, i8 17>, <4 x i8> <i8 -1, i8 0, i8 85, i8 170>, <4 x i8> <i8 0, i8 8, i8 9, i8 10>)
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ret <4 x i8> %f
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}
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; Vectors are folded by handling each scalar element individually, so this is the equivalent of 4 scalar tests:
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; extract(concat(0x00, 0xFF) >> 0) = 0xFF
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; extract(concat(0xFF, 0x00) >> 0) = 0x00
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; extract(concat(0x10, 0x55) >> 1) = 0x2A
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; extract(concat(0x11, 0xAA) >> 2) = 0x6A
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define <4 x i8> @fshr_v4i8() {
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; CHECK-LABEL: @fshr_v4i8(
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; CHECK-NEXT: ret <4 x i8> <i8 -1, i8 0, i8 42, i8 106>
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;
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%f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 0, i8 -1, i8 16, i8 17>, <4 x i8> <i8 -1, i8 0, i8 85, i8 170>, <4 x i8> <i8 0, i8 8, i8 9, i8 10>)
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ret <4 x i8> %f
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}
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; Undef handling
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define i32 @fshl_scalar_all_undef() {
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; CHECK-LABEL: @fshl_scalar_all_undef(
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; CHECK-NEXT: ret i32 undef
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;
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%f = call i32 @llvm.fshl.i32(i32 undef, i32 undef, i32 undef)
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ret i32 %f
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}
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define i32 @fshr_scalar_all_undef() {
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; CHECK-LABEL: @fshr_scalar_all_undef(
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; CHECK-NEXT: ret i32 undef
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;
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%f = call i32 @llvm.fshr.i32(i32 undef, i32 undef, i32 undef)
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ret i32 %f
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}
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define i32 @fshl_scalar_undef_shamt() {
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; CHECK-LABEL: @fshl_scalar_undef_shamt(
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; CHECK-NEXT: ret i32 1
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;
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%f = call i32 @llvm.fshl.i32(i32 1, i32 2, i32 undef)
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ret i32 %f
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}
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define i32 @fshr_scalar_undef_shamt() {
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; CHECK-LABEL: @fshr_scalar_undef_shamt(
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; CHECK-NEXT: ret i32 2
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;
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%f = call i32 @llvm.fshr.i32(i32 1, i32 2, i32 undef)
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ret i32 %f
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}
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define i32 @fshl_scalar_undef_ops() {
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; CHECK-LABEL: @fshl_scalar_undef_ops(
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; CHECK-NEXT: ret i32 undef
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;
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%f = call i32 @llvm.fshl.i32(i32 undef, i32 undef, i32 7)
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ret i32 %f
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}
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define i32 @fshr_scalar_undef_ops() {
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; CHECK-LABEL: @fshr_scalar_undef_ops(
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; CHECK-NEXT: ret i32 undef
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;
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%f = call i32 @llvm.fshr.i32(i32 undef, i32 undef, i32 7)
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ret i32 %f
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}
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define i32 @fshl_scalar_undef_op1_zero_shift() {
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; CHECK-LABEL: @fshl_scalar_undef_op1_zero_shift(
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; CHECK-NEXT: ret i32 undef
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;
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%f = call i32 @llvm.fshl.i32(i32 undef, i32 1, i32 0)
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ret i32 %f
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}
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define i32 @fshl_scalar_undef_op2_zero_shift() {
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; CHECK-LABEL: @fshl_scalar_undef_op2_zero_shift(
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; CHECK-NEXT: ret i32 1
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;
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%f = call i32 @llvm.fshl.i32(i32 1, i32 undef, i32 32)
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ret i32 %f
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}
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define i32 @fshr_scalar_undef_op1_zero_shift() {
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; CHECK-LABEL: @fshr_scalar_undef_op1_zero_shift(
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; CHECK-NEXT: ret i32 1
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;
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%f = call i32 @llvm.fshr.i32(i32 undef, i32 1, i32 64)
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ret i32 %f
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}
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define i32 @fshr_scalar_undef_op2_zero_shift() {
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; CHECK-LABEL: @fshr_scalar_undef_op2_zero_shift(
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; CHECK-NEXT: ret i32 undef
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;
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%f = call i32 @llvm.fshr.i32(i32 1, i32 undef, i32 0)
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ret i32 %f
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}
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define i32 @fshl_scalar_undef_op1_nonzero_shift() {
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; CHECK-LABEL: @fshl_scalar_undef_op1_nonzero_shift(
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; CHECK-NEXT: ret i32 255
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;
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%f = call i32 @llvm.fshl.i32(i32 undef, i32 -1, i32 8)
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ret i32 %f
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}
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define i32 @fshl_scalar_undef_op2_nonzero_shift() {
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; CHECK-LABEL: @fshl_scalar_undef_op2_nonzero_shift(
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; CHECK-NEXT: ret i32 -256
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;
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%f = call i32 @llvm.fshl.i32(i32 -1, i32 undef, i32 8)
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ret i32 %f
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}
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define i32 @fshr_scalar_undef_op1_nonzero_shift() {
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; CHECK-LABEL: @fshr_scalar_undef_op1_nonzero_shift(
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; CHECK-NEXT: ret i32 16777215
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;
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%f = call i32 @llvm.fshr.i32(i32 undef, i32 -1, i32 8)
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ret i32 %f
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}
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define i32 @fshr_scalar_undef_op2_nonzero_shift() {
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; CHECK-LABEL: @fshr_scalar_undef_op2_nonzero_shift(
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; CHECK-NEXT: ret i32 -16777216
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;
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%f = call i32 @llvm.fshr.i32(i32 -1, i32 undef, i32 8)
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ret i32 %f
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}
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; Undef/Undef/Undef; 1/2/Undef; Undef/Undef/3; Undef/1/0
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define <4 x i8> @fshl_vector_mix1() {
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; CHECK-LABEL: @fshl_vector_mix1(
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; CHECK-NEXT: ret <4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>
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;
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%f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>, <4 x i8> <i8 undef, i8 2, i8 undef, i8 1>, <4 x i8> <i8 undef, i8 undef, i8 3, i8 0>)
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ret <4 x i8> %f
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}
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; 1/Undef/8; Undef/-1/2; -1/Undef/2; 7/8/4
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define <4 x i8> @fshl_vector_mix2() {
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; CHECK-LABEL: @fshl_vector_mix2(
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; CHECK-NEXT: ret <4 x i8> <i8 1, i8 3, i8 -4, i8 112>
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;
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%f = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> <i8 1, i8 undef, i8 -1, i8 7>, <4 x i8> <i8 undef, i8 -1, i8 undef, i8 8>, <4 x i8> <i8 8, i8 2, i8 2, i8 4>)
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ret <4 x i8> %f
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}
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; Undef/Undef/Undef; 1/2/Undef; Undef/Undef/3; Undef/1/0
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define <4 x i8> @fshr_vector_mix1() {
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; CHECK-LABEL: @fshr_vector_mix1(
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; CHECK-NEXT: ret <4 x i8> <i8 undef, i8 2, i8 undef, i8 1>
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;
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%f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 undef, i8 1, i8 undef, i8 undef>, <4 x i8> <i8 undef, i8 2, i8 undef, i8 1>, <4 x i8> <i8 undef, i8 undef, i8 3, i8 0>)
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ret <4 x i8> %f
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}
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; 1/Undef/8; Undef/-1/2; -1/Undef/2; 7/8/4
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define <4 x i8> @fshr_vector_mix2() {
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; CHECK-LABEL: @fshr_vector_mix2(
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; CHECK-NEXT: ret <4 x i8> <i8 undef, i8 63, i8 -64, i8 112>
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;
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%f = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> <i8 1, i8 undef, i8 -1, i8 7>, <4 x i8> <i8 undef, i8 -1, i8 undef, i8 8>, <4 x i8> <i8 8, i8 2, i8 2, i8 4>)
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ret <4 x i8> %f
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}
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