182 lines
6.4 KiB
Plaintext
182 lines
6.4 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_fcmp_dead_cc
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $s0, $s1
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; CHECK-LABEL: name: test_fcmp_dead_cc
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; CHECK: liveins: $w1, $x0, $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr32 = COPY $s0
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%4:fpr32 = COPY $s1
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%26:gpr32 = COPY $wzr
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FCMPSrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPSrr %3, %4, implicit-def $nzcv
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%14:gpr32common = UBFMWri %12, 1, 31
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%60:gpr32 = MOVi32imm 1
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%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
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$w0 = COPY %16
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RET_ReallyLR implicit $w0
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...
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---
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name: test_fcmp_64_dead_cc
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $d0, $d1
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; CHECK-LABEL: name: test_fcmp_64_dead_cc
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; CHECK: liveins: $w1, $x0, $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr64 = COPY $d0
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%4:fpr64 = COPY $d1
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%26:gpr32 = COPY $wzr
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FCMPDrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPDrr %3, %4, implicit-def $nzcv
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%14:gpr32common = UBFMWri %12, 1, 31
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%60:gpr32 = MOVi32imm 1
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%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
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$w0 = COPY %16
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RET_ReallyLR implicit $w0
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...
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---
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name: test_fcmp_dead_cc_3_fcmps
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $s0, $s1
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; CHECK-LABEL: name: test_fcmp_dead_cc_3_fcmps
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; CHECK: liveins: $w1, $x0, $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv
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; CHECK: [[SUBWrr1:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr1]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr32 = COPY $s0
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%4:fpr32 = COPY $s1
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%26:gpr32 = COPY $wzr
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FCMPSrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPSrr %3, %4, implicit-def $nzcv
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPSrr %3, %4, implicit-def $nzcv
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%14:gpr32common = UBFMWri %12, 1, 31
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%60:gpr32 = MOVi32imm 1
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%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
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$w0 = COPY %16
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RET_ReallyLR implicit $w0
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...
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---
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name: test_impdef_made_dead
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alignment: 4
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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bb.1:
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liveins: $w1, $x0, $s0, $s1
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; Check that any dead imp-defs of NZCV are marked as such.
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; CHECK-LABEL: name: test_impdef_made_dead
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; CHECK: liveins: $w1, $x0, $s0, $s1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
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; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY4]], implicit-def dead $nzcv
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; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBSWrr]], 1, 31
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
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; CHECK: %ret:gpr32 = SUBSWrr [[CSELWr]], [[SUBSWrr]], implicit-def dead $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr64 = COPY $x0
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%2:gpr32 = COPY $w1
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%3:fpr32 = COPY $s0
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%4:fpr32 = COPY $s1
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%26:gpr32 = COPY $wzr
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%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
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FCMPSrr %3, %4, implicit-def $nzcv
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%14:gpr32common = UBFMWri %12, 1, 31
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%60:gpr32 = MOVi32imm 1
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%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
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%ret:gpr32 = SUBSWrr %16, %12, implicit-def $nzcv
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$w0 = COPY %16
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RET_ReallyLR implicit $w0
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...
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