# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s --- name: test_fcmp_dead_cc alignment: 4 legalized: true regBankSelected: true selected: true tracksRegLiveness: true liveins: - { reg: '$x0' } - { reg: '$w1' } body: | bb.1: liveins: $w1, $x0, $s0, $s1 ; CHECK-LABEL: name: test_fcmp_dead_cc ; CHECK: liveins: $w1, $x0, $s0, $s1 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1 ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv ; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]] ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 %1:gpr64 = COPY $x0 %2:gpr32 = COPY $w1 %3:fpr32 = COPY $s0 %4:fpr32 = COPY $s1 %26:gpr32 = COPY $wzr FCMPSrr %3, %4, implicit-def $nzcv %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv FCMPSrr %3, %4, implicit-def $nzcv %14:gpr32common = UBFMWri %12, 1, 31 %60:gpr32 = MOVi32imm 1 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv $w0 = COPY %16 RET_ReallyLR implicit $w0 ... --- name: test_fcmp_64_dead_cc alignment: 4 legalized: true regBankSelected: true selected: true tracksRegLiveness: true liveins: - { reg: '$x0' } - { reg: '$w1' } body: | bb.1: liveins: $w1, $x0, $d0, $d1 ; CHECK-LABEL: name: test_fcmp_64_dead_cc ; CHECK: liveins: $w1, $x0, $d0, $d1 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv ; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]] ; CHECK: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 %1:gpr64 = COPY $x0 %2:gpr32 = COPY $w1 %3:fpr64 = COPY $d0 %4:fpr64 = COPY $d1 %26:gpr32 = COPY $wzr FCMPDrr %3, %4, implicit-def $nzcv %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv FCMPDrr %3, %4, implicit-def $nzcv %14:gpr32common = UBFMWri %12, 1, 31 %60:gpr32 = MOVi32imm 1 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv $w0 = COPY %16 RET_ReallyLR implicit $w0 ... --- name: test_fcmp_dead_cc_3_fcmps alignment: 4 legalized: true regBankSelected: true selected: true tracksRegLiveness: true liveins: - { reg: '$x0' } - { reg: '$w1' } body: | bb.1: liveins: $w1, $x0, $s0, $s1 ; CHECK-LABEL: name: test_fcmp_dead_cc_3_fcmps ; CHECK: liveins: $w1, $x0, $s0, $s1 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1 ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv ; CHECK: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]] ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv ; CHECK: [[SUBWrr1:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]] ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr1]], 1, 31 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 %1:gpr64 = COPY $x0 %2:gpr32 = COPY $w1 %3:fpr32 = COPY $s0 %4:fpr32 = COPY $s1 %26:gpr32 = COPY $wzr FCMPSrr %3, %4, implicit-def $nzcv %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv FCMPSrr %3, %4, implicit-def $nzcv %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv FCMPSrr %3, %4, implicit-def $nzcv %14:gpr32common = UBFMWri %12, 1, 31 %60:gpr32 = MOVi32imm 1 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv $w0 = COPY %16 RET_ReallyLR implicit $w0 ... --- name: test_impdef_made_dead alignment: 4 legalized: true regBankSelected: true selected: true tracksRegLiveness: true liveins: - { reg: '$x0' } - { reg: '$w1' } body: | bb.1: liveins: $w1, $x0, $s0, $s1 ; Check that any dead imp-defs of NZCV are marked as such. ; CHECK-LABEL: name: test_impdef_made_dead ; CHECK: liveins: $w1, $x0, $s0, $s1 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1 ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY1]], [[COPY4]], implicit-def dead $nzcv ; CHECK: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBSWrr]], 1, 31 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv ; CHECK: %ret:gpr32 = SUBSWrr [[CSELWr]], [[SUBSWrr]], implicit-def dead $nzcv ; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: RET_ReallyLR implicit $w0 %1:gpr64 = COPY $x0 %2:gpr32 = COPY $w1 %3:fpr32 = COPY $s0 %4:fpr32 = COPY $s1 %26:gpr32 = COPY $wzr %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv FCMPSrr %3, %4, implicit-def $nzcv %14:gpr32common = UBFMWri %12, 1, 31 %60:gpr32 = MOVi32imm 1 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv %ret:gpr32 = SUBSWrr %16, %12, implicit-def $nzcv $w0 = COPY %16 RET_ReallyLR implicit $w0 ...