59 lines
2.3 KiB
LLVM
59 lines
2.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,SPLITTING
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; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,MISALIGNED
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@g0 = external dso_local global <3 x float>, align 16
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@g1 = external dso_local global <3 x float>, align 4
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define void @blam() {
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; SPLITTING-LABEL: blam:
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; SPLITTING: // %bb.0:
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; SPLITTING-NEXT: adrp x8, g1
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; SPLITTING-NEXT: add x8, x8, :lo12:g1
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; SPLITTING-NEXT: adrp x9, g0
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; SPLITTING-NEXT: ldr q0, [x9, :lo12:g0]
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; SPLITTING-NEXT: str d0, [x8]
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; SPLITTING-NEXT: ret
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;
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; MISALIGNED-LABEL: blam:
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; MISALIGNED: // %bb.0:
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; MISALIGNED-NEXT: adrp x8, g0
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; MISALIGNED-NEXT: ldr q0, [x8, :lo12:g0]
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; MISALIGNED-NEXT: adrp x8, g1
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; MISALIGNED-NEXT: add x8, x8, :lo12:g1
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; MISALIGNED-NEXT: str d0, [x8]
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; MISALIGNED-NEXT: ret
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%tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
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%tmp5 = load <3 x float>, <3 x float>* @g0, align 16
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%tmp6 = extractelement <3 x float> %tmp5, i64 0
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store float %tmp6, float* %tmp4
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%tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
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%tmp8 = load <3 x float>, <3 x float>* @g0, align 16
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%tmp9 = extractelement <3 x float> %tmp8, i64 1
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store float %tmp9, float* %tmp7
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ret void;
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}
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; PR21711 - Merge vector stores into wider vector stores.
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; On Cyclone, the stores should not get merged into a 16-byte store because
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; unaligned 16-byte stores are slow. This test would infinite loop when
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; the fastness of unaligned accesses was not specified correctly.
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define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
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; CHECK-LABEL: merge_vec_extract_stores:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stur q0, [x0, #24]
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; CHECK-NEXT: ret
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%idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
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%idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4
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%shuffle0 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%shuffle1 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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store <2 x float> %shuffle0, <2 x float>* %idx0, align 8
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store <2 x float> %shuffle1, <2 x float>* %idx1, align 8
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ret void
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}
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