326 lines
12 KiB
C++
326 lines
12 KiB
C++
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//===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86SelectionDAGInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86SelectionDAGInfo.h"
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#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/DerivedTypes.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-selectiondag-info"
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static cl::opt<bool>
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UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false),
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cl::desc("Use fast short rep mov in memcpy lowering"));
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bool X86SelectionDAGInfo::isBaseRegConflictPossible(
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SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
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// We cannot use TRI->hasBasePointer() until *after* we select all basic
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// blocks. Legalization may introduce new stack temporaries with large
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// alignment requirements. Fall back to generic code if there are any
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// dynamic stack adjustments (hopefully rare) and the base pointer would
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// conflict if we had to use it.
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MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
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if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
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return false;
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const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
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DAG.getSubtarget().getRegisterInfo());
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Register BaseReg = TRI->getBaseRegister();
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for (unsigned R : ClobberSet)
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if (BaseReg == R)
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return true;
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return false;
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}
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SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
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SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
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SDValue Size, Align Alignment, bool isVolatile,
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MachinePointerInfo DstPtrInfo) const {
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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const X86Subtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<X86Subtarget>();
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#ifndef NDEBUG
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// If the base register might conflict with our physical registers, bail out.
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const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
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X86::ECX, X86::EAX, X86::EDI};
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assert(!isBaseRegConflictPossible(DAG, ClobberSet));
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#endif
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// If to a segment-relative address space, use the default lowering.
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if (DstPtrInfo.getAddrSpace() >= 256)
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return SDValue();
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// If not DWORD aligned or size is more than the threshold, call the library.
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// The libc version is likely to be faster for these cases. It can use the
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// address value and run time information about the CPU.
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if (Alignment < Align(4) || !ConstantSize ||
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ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
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// Check to see if there is a specialized entry-point for memory zeroing.
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ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Val);
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if (const char *bzeroName = (ValC && ValC->isNullValue())
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? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO)
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: nullptr) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
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Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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Entry.Node = Dst;
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Entry.Ty = IntPtrTy;
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Args.push_back(Entry);
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Entry.Node = Size;
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Args.push_back(Entry);
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TargetLowering::CallLoweringInfo CLI(DAG);
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CLI.setDebugLoc(dl)
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.setChain(Chain)
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.setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
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DAG.getExternalSymbol(bzeroName, IntPtr),
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std::move(Args))
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.setDiscardResult();
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std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI);
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return CallResult.second;
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}
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// Otherwise have the target-independent code call memset.
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return SDValue();
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}
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uint64_t SizeVal = ConstantSize->getZExtValue();
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SDValue InFlag;
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EVT AVT;
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SDValue Count;
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ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Val);
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unsigned BytesLeft = 0;
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if (ValC) {
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unsigned ValReg;
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uint64_t Val = ValC->getZExtValue() & 255;
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// If the value is a constant, then we can potentially use larger sets.
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if (Alignment > Align(2)) {
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// DWORD aligned
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AVT = MVT::i32;
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ValReg = X86::EAX;
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Val = (Val << 8) | Val;
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Val = (Val << 16) | Val;
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if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
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AVT = MVT::i64;
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ValReg = X86::RAX;
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Val = (Val << 32) | Val;
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}
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} else if (Alignment == Align(2)) {
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// WORD aligned
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AVT = MVT::i16;
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ValReg = X86::AX;
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Val = (Val << 8) | Val;
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} else {
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// Byte aligned
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AVT = MVT::i8;
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ValReg = X86::AL;
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Count = DAG.getIntPtrConstant(SizeVal, dl);
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}
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if (AVT.bitsGT(MVT::i8)) {
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unsigned UBytes = AVT.getSizeInBits() / 8;
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Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
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BytesLeft = SizeVal % UBytes;
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}
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Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
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InFlag);
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InFlag = Chain.getValue(1);
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} else {
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AVT = MVT::i8;
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Count = DAG.getIntPtrConstant(SizeVal, dl);
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Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Val, InFlag);
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InFlag = Chain.getValue(1);
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}
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bool Use64BitRegs = Subtarget.isTarget64BitLP64();
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Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX,
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Count, InFlag);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RDI : X86::EDI,
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Dst, InFlag);
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InFlag = Chain.getValue(1);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
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Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
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if (BytesLeft) {
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// Handle the last 1 - 7 bytes.
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unsigned Offset = SizeVal - BytesLeft;
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EVT AddrVT = Dst.getValueType();
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EVT SizeVT = Size.getValueType();
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Chain =
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DAG.getMemset(Chain, dl,
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DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
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DAG.getConstant(Offset, dl, AddrVT)),
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Val, DAG.getConstant(BytesLeft, dl, SizeVT), Alignment,
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isVolatile, false, DstPtrInfo.getWithOffset(Offset));
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}
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// TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
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return Chain;
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}
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/// Emit a single REP MOVS{B,W,D,Q} instruction.
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static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG,
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const SDLoc &dl, SDValue Chain, SDValue Dst,
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SDValue Src, SDValue Size, MVT AVT) {
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const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
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const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX;
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const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
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const unsigned SI = Use64BitRegs ? X86::RSI : X86::ESI;
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SDValue InFlag;
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Chain = DAG.getCopyToReg(Chain, dl, CX, Size, InFlag);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, DI, Dst, InFlag);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, SI, Src, InFlag);
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InFlag = Chain.getValue(1);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = {Chain, DAG.getValueType(AVT), InFlag};
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return DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
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}
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/// Emit a single REP MOVSB instruction for a particular constant size.
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static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
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const SDLoc &dl, SDValue Chain, SDValue Dst,
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SDValue Src, uint64_t Size) {
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return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
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DAG.getIntPtrConstant(Size, dl), MVT::i8);
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}
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/// Returns the best type to use with repmovs depending on alignment.
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static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget,
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uint64_t Align) {
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assert((Align != 0) && "Align is normalized");
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assert(isPowerOf2_64(Align) && "Align is a power of 2");
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switch (Align) {
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case 1:
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return MVT::i8;
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case 2:
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return MVT::i16;
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case 4:
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return MVT::i32;
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default:
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return Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
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}
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}
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/// Returns a REP MOVS instruction, possibly with a few load/stores to implement
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/// a constant size memory copy. In some cases where we know REP MOVS is
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/// inefficient we return an empty SDValue so the calling code can either
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/// generate a load/store sequence or call the runtime memcpy function.
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static SDValue emitConstantSizeRepmov(
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SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl,
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SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT,
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unsigned Align, bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) {
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/// TODO: Revisit next line: big copy with ERMSB on march >= haswell are very
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/// efficient.
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if (!AlwaysInline && Size > Subtarget.getMaxInlineSizeThreshold())
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return SDValue();
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/// If we have enhanced repmovs we use it.
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if (Subtarget.hasERMSB())
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return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
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assert(!Subtarget.hasERMSB() && "No efficient RepMovs");
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/// We assume runtime memcpy will do a better job for unaligned copies when
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/// ERMS is not present.
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if (!AlwaysInline && (Align & 3) != 0)
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return SDValue();
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const MVT BlockType = getOptimalRepmovsType(Subtarget, Align);
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const uint64_t BlockBytes = BlockType.getSizeInBits() / 8;
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const uint64_t BlockCount = Size / BlockBytes;
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const uint64_t BytesLeft = Size % BlockBytes;
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SDValue RepMovs =
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emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
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DAG.getIntPtrConstant(BlockCount, dl), BlockType);
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/// RepMov can process the whole length.
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if (BytesLeft == 0)
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return RepMovs;
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assert(BytesLeft && "We have leftover at this point");
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/// In case we optimize for size we use repmovsb even if it's less efficient
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/// so we can save the loads/stores of the leftover.
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
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// Handle the last 1 - 7 bytes.
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SmallVector<SDValue, 4> Results;
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Results.push_back(RepMovs);
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unsigned Offset = Size - BytesLeft;
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EVT DstVT = Dst.getValueType();
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EVT SrcVT = Src.getValueType();
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Results.push_back(DAG.getMemcpy(
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Chain, dl,
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DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
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DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
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DAG.getConstant(BytesLeft, dl, SizeVT), llvm::Align(Align), isVolatile,
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/*AlwaysInline*/ true, /*isTailCall*/ false,
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DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset)));
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
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}
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SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
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SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
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// If to a segment-relative address space, use the default lowering.
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if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256)
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return SDValue();
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// If the base registers conflict with our physical registers, use the default
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// lowering.
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const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
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X86::ECX, X86::ESI, X86::EDI};
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if (isBaseRegConflictPossible(DAG, ClobberSet))
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return SDValue();
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const X86Subtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<X86Subtarget>();
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// If enabled and available, use fast short rep mov.
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if (UseFSRMForMemcpy && Subtarget.hasFSRM())
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return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8);
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/// Handle constant sizes,
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if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size))
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return emitConstantSizeRepmov(
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DAG, Subtarget, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
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Size.getValueType(), Alignment.value(), isVolatile, AlwaysInline,
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DstPtrInfo, SrcPtrInfo);
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return SDValue();
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}
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