SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fix read_reg

Browse Source
This commit is contained in:
Andrea Fioraldi 2021-07-06 14:29:56 +02:00
parent d4d652ed9b
commit e407657da0
5 changed files with 28 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
cpu.c
View File

@ -63,10 +63,6 @@ int libafl_qemu_write_reg(int reg, uint8_t* val)
return 0; return 0;
} }
if (libafl_qemu_mem_buf == NULL) {
libafl_qemu_mem_buf = g_byte_array_sized_new(64);
}
CPUClass *cc = CPU_GET_CLASS(cpu); CPUClass *cc = CPU_GET_CLASS(cpu);
if (reg < cc->gdb_num_core_regs) { if (reg < cc->gdb_num_core_regs) {
return cc->gdb_write_register(cpu, val, reg); return cc->gdb_write_register(cpu, val, reg);
@ -81,6 +77,10 @@ int libafl_qemu_read_reg(int reg, uint8_t* val)
return 0; return 0;
} }
if (libafl_qemu_mem_buf == NULL) {
libafl_qemu_mem_buf = g_byte_array_sized_new(64);
}
CPUClass *cc = CPU_GET_CLASS(cpu); CPUClass *cc = CPU_GET_CLASS(cpu);
if (reg < cc->gdb_num_core_regs) { if (reg < cc->gdb_num_core_regs) {
int len = cc->gdb_read_register(cpu, libafl_qemu_mem_buf, reg); int len = cc->gdb_read_register(cpu, libafl_qemu_mem_buf, reg);

2
qemu_libafl_bridge/Cargo.toml
View File

@ -1,6 +1,6 @@
[package] [package]
name = "qemu_libafl_bridge" name = "qemu_libafl_bridge"
version = "0.2.1" version = "0.2.2"
authors = ["Andrea Fioraldi <andreafioraldi@gmail.com>"] authors = ["Andrea Fioraldi <andreafioraldi@gmail.com>"]
description = "QEMU and LibAFL bridge lib" description = "QEMU and LibAFL bridge lib"
repository = "https://github.com/AFLplusplus/qemu-libafl-bridge/" repository = "https://github.com/AFLplusplus/qemu-libafl-bridge/"

14
qemu_libafl_bridge/src/amd64.rs
View File

@ -5,13 +5,13 @@ use num_enum::{IntoPrimitive, TryFromPrimitive};
#[allow(clippy::pub_enum_variant_names)] #[allow(clippy::pub_enum_variant_names)]
pub enum Amd64Regs { pub enum Amd64Regs {
Rax = 0, Rax = 0,
Rcx = 1, Rbx = 1,
Rdx = 2, Rcx = 2,
Rbx = 3, Rdx = 3,
Rsp = 4, Rsi = 4,
Rbp = 5, Rdi = 5,
Rsi = 6, Rbp = 6,
Rdi = 7, Rsp = 7,
R8 = 8, R8 = 8,
R9 = 9, R9 = 9,
R10 = 10, R10 = 10,

1
qemu_libafl_bridge/src/lib.rs
View File

@ -2,6 +2,7 @@ use core::{mem::transmute, ptr::copy_nonoverlapping};
use num::Num; use num::Num;
pub mod amd64; pub mod amd64;
pub mod x86;
/* /*
int libafl_qemu_write_reg(int reg, uint8_t* val); int libafl_qemu_write_reg(int reg, uint8_t* val);

15
qemu_libafl_bridge/src/x86.rs Normal file
View File

@ -0,0 +1,15 @@
use num_enum::{IntoPrimitive, TryFromPrimitive};
#[derive(IntoPrimitive, TryFromPrimitive, Clone, Copy)]
#[repr(i32)]
#[allow(clippy::pub_enum_variant_names)]
pub enum X86Regs {
Eax = 0,
Ebx = 1,
Ecx = 2,
Edx = 3,
Esi = 4,
Edi = 5,
Ebp = 6,
Esp = 7,
}