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target-arm: make IFAR/DFAR banked

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When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-22-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabian Aggeler 2014-12-11 12:07:51 +00:00 committed by Peter Maydell
parent 4a7e2d7315
commit b848ce2b9c
3 changed files with 28 additions and 9 deletions
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2
target-arm/cpu.c
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@ -552,7 +552,7 @@ static void arm1026_initfn(Object *obj)
ARMCPRegInfo ifar = { ARMCPRegInfo ifar = {
.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .access = PL1_RW,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
.resetvalue = 0 .resetvalue = 0
}; };
define_one_arm_cp_reg(cpu, &ifar); define_one_arm_cp_reg(cpu, &ifar);

19
target-arm/cpu.h
View File

@ -261,7 +261,24 @@ typedef struct CPUARMState {
uint64_t esr_el[4]; uint64_t esr_el[4];
}; };
uint32_t c6_region[8]; /* MPU base/size registers. */ uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[4]; /* Fault address registers. */ union { /* Fault address registers. */
struct {
uint64_t _unused_far0;
#ifdef HOST_WORDS_BIGENDIAN
uint32_t ifar_ns;
uint32_t dfar_ns;
uint32_t ifar_s;
uint32_t dfar_s;
#else
uint32_t dfar_ns;
uint32_t ifar_ns;
uint32_t dfar_s;
uint32_t ifar_s;
#endif
uint64_t _unused_far3;
};
uint64_t far_el[4];
};
uint64_t par_el1; /* Translation result. */ uint64_t par_el1; /* Translation result. */
uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data; uint32_t c9_data;

16
target-arm/helper.c
View File

@ -559,7 +559,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
.access = PL0_W, .type = ARM_CP_NOP }, .access = PL0_W, .type = ARM_CP_NOP },
{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW, .access = PL1_RW,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
offsetof(CPUARMState, cp15.ifar_ns) },
.resetvalue = 0, }, .resetvalue = 0, },
/* Watchpoint Fault Address Register : should actually only be present /* Watchpoint Fault Address Register : should actually only be present
* for 1136, 1176, 11MPCore. * for 1136, 1176, 11MPCore.
@ -1682,11 +1683,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
/* 64-bit FAR; this entry also gives us the AArch32 DFAR */ { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
{ .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
.resetvalue = 0, }, .resetvalue = 0, },
{ .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
.access = PL1_RW, .resetvalue = 0,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
offsetof(CPUARMState, cp15.dfar_ns) } },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
@ -4330,8 +4334,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Fall through to prefetch abort. */ /* Fall through to prefetch abort. */
case EXCP_PREFETCH_ABORT: case EXCP_PREFETCH_ABORT:
A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
env->exception.fsr, (uint32_t)env->exception.vaddress); env->exception.fsr, (uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT; new_mode = ARM_CPU_MODE_ABT;
@ -4341,8 +4344,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
break; break;
case EXCP_DATA_ABORT: case EXCP_DATA_ABORT:
A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
env->exception.fsr, env->exception.fsr,
(uint32_t)env->exception.vaddress); (uint32_t)env->exception.vaddress);