SYS-OSS/FRET-LibAFL
4
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix compile error

Browse Source
This commit is contained in:
Omree 2021-05-09 18:12:13 +03:00
parent 85a90c7d21
commit 8b2e86e7e6
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
libafl_frida/src/helper.rs
View File

@ -424,7 +424,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
writer.put_ldr_reg_u64(Aarch64Register::X0, value); writer.put_ldr_reg_u64(Aarch64Register::X0, value);
} }
CmplogOperandType::Regid(reg) => { CmplogOperandType::Regid(reg) => {
let reg = self.get_writer_register(reg); let reg = self.writer_register(reg);
match reg { match reg {
Aarch64Register::X0 | Aarch64Register::W0 => {} Aarch64Register::X0 | Aarch64Register::W0 => {}
Aarch64Register::X1 | Aarch64Register::W1 => { Aarch64Register::X1 | Aarch64Register::W1 => {
@ -438,9 +438,9 @@ impl<'a> FridaInstrumentationHelper<'a> {
} }
} }
CmplogOperandType::Mem(basereg, indexreg, displacement, width) => { CmplogOperandType::Mem(basereg, indexreg, displacement, width) => {
let basereg = self.get_writer_register(basereg); let basereg = self.writer_register(basereg);
let indexreg = if indexreg.0 != 0 { let indexreg = if indexreg.0 != 0 {
Some(self.get_writer_register(indexreg)) Some(self.writer_register(indexreg))
} else { } else {
None None
}; };
@ -489,7 +489,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
writer.put_ldr_reg_u64(Aarch64Register::X1, value); writer.put_ldr_reg_u64(Aarch64Register::X1, value);
} }
CmplogOperandType::Regid(reg) => { CmplogOperandType::Regid(reg) => {
let reg = self.get_writer_register(reg); let reg = self.writer_register(reg);
match reg { match reg {
Aarch64Register::X1 | Aarch64Register::W1 => {} Aarch64Register::X1 | Aarch64Register::W1 => {}
Aarch64Register::X0 | Aarch64Register::W0 => { Aarch64Register::X0 | Aarch64Register::W0 => {
@ -507,9 +507,9 @@ impl<'a> FridaInstrumentationHelper<'a> {
} }
} }
CmplogOperandType::Mem(basereg, indexreg, displacement, width) => { CmplogOperandType::Mem(basereg, indexreg, displacement, width) => {
let basereg = self.get_writer_register(basereg); let basereg = self.writer_register(basereg);
let indexreg = if indexreg.0 != 0 { let indexreg = if indexreg.0 != 0 {
Some(self.get_writer_register(indexreg)) Some(self.writer_register(indexreg))
} else { } else {
None None
}; };
@ -1059,7 +1059,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
opmem.base(), opmem.base(),
opmem.index(), opmem.index(),
opmem.disp(), opmem.disp(),
self.get_instruction_width(instr, &operands), self.instruction_width(instr, &operands),
)), )),
Arm64OperandType::Cimm(val) => Some(CmplogOperandType::Cimm(val as u64)), Arm64OperandType::Cimm(val) => Some(CmplogOperandType::Cimm(val as u64)),
_ => return Err(()), _ => return Err(()),
@ -1076,7 +1076,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
opmem.base(), opmem.base(),
opmem.index(), opmem.index(),
opmem.disp(), opmem.disp(),
self.get_instruction_width(instr, &operands), self.instruction_width(instr, &operands),
)), )),
Arm64OperandType::Cimm(val) => Some(CmplogOperandType::Cimm(val as u64)), Arm64OperandType::Cimm(val) => Some(CmplogOperandType::Cimm(val as u64)),
_ => return Err(()), _ => return Err(()),