forked from alwin.berger/FRET-qemu

Fix a bug on the ARM GIC model where interrupts are not set pending on the correct target CPUs when they are triggered by writes to the Interrupt Set Enable or Set Pending registers. Signed-off-by: Daniel Sangorrin <dsl@ertl.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Read the documentation in qemu-doc.html or on http://wiki.qemu.org - QEMU team
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