Wilfred Mallawa 9972479fac riscv: opentitan: Connect opentitan SPI Host ...

Connect spi host[1/0] to opentitan.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-04-22 10:35:16 +10:00

..

boot.c

Remove qemu-common.h include from most units

2022-04-06 14:31:55 +02:00

Kconfig

hw/riscv: virt: Add optional AIA IMSIC support to virt machine

2022-03-03 13:14:50 +10:00

meson.build

hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines

2021-07-20 15:32:49 +02:00

microchip_pfsoc.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

riscv: opentitan: Connect opentitan SPI Host

2022-04-22 10:35:16 +10:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_e.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

sifive_u.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

spike.c

hw/riscv: Remove macros for ELF BIOS image names

2022-01-21 15:52:57 +10:00

virt.c

hw/riscv: virt: Increase maximum number of allowed CPUs

2022-03-03 13:14:50 +10:00