Jean-Christophe DUBOIS
ec46eaa83a
i.MX: Add i.MX6 SOC implementation.
For now we only support the following devices:
* up to 4 Cortex A9 cores
* A9 MPCORE (SCU, GIC, TWD)
* 5 i.MX UARTs
* 2 EPIT timers
* 1 GPT timer
* 3 I2C controllers
* 7 GPIO controllers
* 6 SDHC controllers
* 5 SPI controllers
* 1 CCM device
* 1 SRC device
* various ROM/RAM areas.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-05-12 13:22:29 +01:00
..
2015-11-06 14:09:01 -05:00
2016-03-04 11:30:21 +00:00
2016-03-16 17:42:18 +00:00
2016-03-16 17:42:18 +00:00
2016-02-03 15:00:46 +00:00
2013-12-17 20:12:51 +00:00
2014-02-14 16:22:31 +01:00
2015-06-19 14:17:44 +01:00
2016-05-12 13:22:29 +01:00
2015-12-17 13:37:16 +00:00
2015-12-17 13:37:15 +00:00
2015-09-08 17:38:43 +01:00
2014-10-20 14:02:25 +02:00
2013-04-08 18:13:10 +02:00
2014-10-20 14:02:25 +02:00
2016-02-03 15:00:45 +00:00
2013-04-08 18:13:10 +02:00
2013-04-08 18:13:10 +02:00
2015-04-13 11:37:10 +01:00
2015-06-02 15:44:28 +01:00
2016-02-03 13:46:34 +00:00
2016-03-04 11:30:17 +00:00
2016-01-21 14:15:03 +00:00