ths 19221bdaf8 Update comment. We can't easily adhere to the architecture spec because ...

it would involve counting the actually executed instructions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2708 c046a42c-6fe2-441c-8c8c-71466251a162

2007-04-19 16:35:09 +00:00

..

cpu.h

Choose number of TLBs at runtime, by Herve Poussineau.

2007-04-17 15:26:47 +00:00

exec.h

Fix qemu SIGFPE caused by division-by-zero due to underflow.

2007-04-15 21:21:33 +00:00

fop_template.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

helper.c

Another fix for CP0 Cause register handling.

2007-04-13 20:17:54 +00:00

mips-defs.h

Update comment. We can't easily adhere to the architecture spec because

2007-04-19 16:35:09 +00:00

op_helper_mem.c

Actually enable 64bit configuration.

2007-04-01 12:36:18 +00:00

op_helper.c

Choose number of TLBs at runtime, by Herve Poussineau.

2007-04-17 15:26:47 +00:00

op_mem.c

Catch unaligned sc/scd.

2007-04-09 14:14:21 +00:00

op_template.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

op.c

Choose number of TLBs at runtime, by Herve Poussineau.

2007-04-17 15:26:47 +00:00

TODO

Update mips TODO.

2007-03-30 18:56:19 +00:00

translate_init.c

Choose number of TLBs at runtime, by Herve Poussineau.

2007-04-17 15:26:47 +00:00

translate.c

Choose number of TLBs at runtime, by Herve Poussineau.

2007-04-17 15:26:47 +00:00