Alex Williamson ea8cfdb5d1 pcie: Add link speed and width fields to PCIESlot
Add fields allowing the PCIe link speed and width of a PCIESlot to
be configured, with an instance_post_init callback on the root port
parent class to set defaults.  This allows child classes to set these
via properties or via their own instance_init callback, without
requiring all implementions to support arbitrary user selected values.

Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-12-19 16:48:16 -05:00
..
2018-12-11 15:45:22 -02:00
2016-10-04 13:28:07 +01:00
2018-11-02 14:03:33 +00:00
2017-01-27 18:07:59 +01:00
2018-10-05 11:26:56 +02:00
2018-12-11 15:45:22 -02:00
2016-05-18 15:04:27 +03:00
2018-12-11 15:45:22 -02:00
2018-12-11 15:45:22 -02:00
2013-04-08 18:13:10 +02:00
2018-12-11 15:45:22 -02:00
2018-02-09 05:05:11 +01:00
2018-12-11 15:45:22 -02:00
2018-06-27 13:01:40 +01:00
2018-02-09 05:05:11 +01:00
2017-01-27 18:07:59 +01:00
2018-06-01 14:15:10 +02:00
2018-12-11 15:45:22 -02:00
2017-06-01 18:49:22 +02:00
2018-12-11 15:45:22 -02:00
2018-12-11 18:28:46 +01:00
2013-04-08 18:13:10 +02:00
2018-12-11 15:45:22 -02:00