Richard Henderson cf0ed30eb1 tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero ...

Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the JIT")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2023-10-22 16:32:28 -07:00

..

tcg-target-con-set.h

tcg/riscv: Support CTZ, CLZ from Zbb

2023-05-25 15:29:36 +00:00

tcg-target-con-str.h

tcg/riscv: Support ANDN, ORN, XNOR from Zbb

2023-05-25 13:57:52 +00:00

tcg-target-reg-bits.h

tcg: Split out tcg-target-reg-bits.h

2023-06-05 12:04:28 -07:00

tcg-target.c.inc

tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero

2023-10-22 16:32:28 -07:00

tcg-target.h

tcg/riscv: Implement negsetcond_*

2023-08-24 11:22:42 -07:00