ths ae2dbf7fb0 Micro-optimize back-to-back store-load sequences. ...

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3743 c046a42c-6fe2-441c-8c8c-71466251a162

2007-11-26 09:01:34 +00:00

..

cpu.h

added cpu_model parameter to cpu_init()

2007-11-10 15:15:54 +00:00

exec.h

Use FORCE_RET, scrap RETURN which was implemented in target-specific code.

2007-11-09 23:09:41 +00:00

fop_template.c

Fix int/float inconsistencies.

2007-11-17 14:53:06 +00:00

helper.c

Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.

2007-11-22 00:34:36 +00:00

mips-defs.h

Clean out the N32 macros from target-mips, and introduce MIPS ABI specific

2007-11-08 18:05:37 +00:00

op_helper.c

Add strict checking mode for softfp code.

2007-11-18 14:33:24 +00:00

op_mem.c

Use FORCE_RET, scrap RETURN which was implemented in target-specific code.

2007-11-09 23:09:41 +00:00

op_template.c

Use FORCE_RET, scrap RETURN which was implemented in target-specific code.

2007-11-09 23:09:41 +00:00

op.c

Fix MIPS64 R2 instructions.

2007-11-18 03:36:07 +00:00

TODO

Update TODO.

2007-10-17 13:43:58 +00:00

translate_init.c

Add older 4Km variants.

2007-11-19 16:10:33 +00:00

translate.c

Micro-optimize back-to-back store-load sequences.

2007-11-26 09:01:34 +00:00