Peter Maydell
a4716fd8d7
Second RISC-V PR for QEMU 6.1
- Update the PLIC and CLINT DT bindings
- Improve documentation for RISC-V machines
- Support direct kernel boot for microchip_pfsoc
- Fix WFI exception behaviour
- Improve CSR printing
- Initial support for the experimental Bit Manip extension
-----BEGIN PGP SIGNATURE-----
iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmC+uasACgkQIeENKd+X
cFTUFwf/TqBBNl8oWFBMTeV+Puwy5s8l9LZpBzWq6W0Wd3y/RyetutMI0v2ir3lC
ezGMLEmGSvYVugDzb2tdZI1DOx/ka8d3mzyU7+Jf8/LA9LCBp0Uj0kVKOw5wL8+V
LoTT6/v0ymEr7Achp4LSpxY//A4BxcCfFRxH83BdUHeybl37UvUpXkaAraGUjfVR
afoB4KQk/IrhT4KtCXnSqr3T/Q9vVHnXhkKOFiR6db3RqWtyq9VDI/lwx/X1Vg+V
iaP/a5IGhfGJP+IHPyEINrp6LPJv8qBl1j0PXhbo2NbIJtZr7lJdB/hmfKOjcHag
r5RtzGVa+JODY4JTTYa1UlXiLVsVHw==
=Dhie
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging
Second RISC-V PR for QEMU 6.1
- Update the PLIC and CLINT DT bindings
- Improve documentation for RISC-V machines
- Support direct kernel boot for microchip_pfsoc
- Fix WFI exception behaviour
- Improve CSR printing
- Initial support for the experimental Bit Manip extension
# gpg: Signature made Tue 08 Jun 2021 01:28:27 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits)
target/riscv: rvb: add b-ext version cpu option
target/riscv: rvb: support and turn on B-extension from command line
target/riscv: rvb: add/shift with prefix zero-extend
target/riscv: rvb: address calculation
target/riscv: rvb: generalized or-combine
target/riscv: rvb: generalized reverse
target/riscv: rvb: rotate (left/right)
target/riscv: rvb: shift ones
target/riscv: rvb: single-bit instructions
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
target/riscv: rvb: sign-extend instructions
target/riscv: rvb: min/max instructions
target/riscv: rvb: pack two words into one register
target/riscv: rvb: logic-with-negate
target/riscv: rvb: count bits set
target/riscv: rvb: count leading/trailing zeros
target/riscv: reformat @sh format encoding for B-extension
target/riscv: Pass the same value to oprsz and maxsz.
target/riscv/pmp: Add assert for ePMP operations
target/riscv: Dump CSR mscratch/sscratch/satp
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-08 13:54:23 +01:00
..
2021-03-22 18:58:19 -04:00
2021-01-12 21:19:02 +00:00
2021-06-03 16:43:25 +01:00
2020-07-10 15:18:08 +02:00
2021-05-02 17:24:50 +02:00
2021-05-13 20:13:24 +01:00
2021-06-03 16:43:27 +01:00
2020-09-18 14:12:32 -04:00
2021-03-19 15:18:43 +01:00
2021-05-12 18:20:25 +02:00
2021-03-08 17:20:04 +00:00
2021-05-14 10:26:18 -04:00
2020-10-27 11:10:32 +00:00
2020-09-18 14:12:32 -04:00
2021-04-15 07:10:39 -05:00
2021-04-30 11:16:51 +01:00
2020-11-15 17:04:40 +01:00
2020-09-22 21:11:10 +01:00
2021-03-15 21:02:20 +01:00
2020-09-18 14:12:32 -04:00
2020-09-18 14:12:32 -04:00
2021-05-04 11:41:25 +10:00
2020-09-30 19:11:36 +02:00
2021-01-19 09:11:52 +01:00
2021-05-14 10:26:18 -04:00
2021-02-21 18:41:04 +01:00
2021-05-10 17:21:54 +01:00
2021-03-05 15:17:34 +00:00
2020-09-18 14:12:32 -04:00
2020-12-08 13:48:57 -05:00
2021-05-04 11:41:25 +10:00
2020-09-18 14:12:32 -04:00
2021-05-05 20:29:14 +01:00
2021-06-03 13:22:06 +10:00
2020-09-09 09:27:09 -04:00
2021-02-10 09:23:28 +00:00
2021-06-08 09:59:42 +10:00
2020-10-18 16:21:42 +01:00
2020-09-09 09:27:09 -04:00
2021-03-26 09:33:50 +01:00
2021-04-12 22:31:24 +01:00
2021-02-21 12:12:18 +00:00
2021-03-06 16:18:42 +01:00
2020-09-09 09:27:09 -04:00
2021-03-19 15:18:43 +01:00
2021-05-01 10:03:52 +02:00
2021-05-02 17:24:50 +02:00
2021-05-18 09:36:21 +01:00
2021-03-15 17:01:12 +01:00
2020-11-23 10:05:58 -07:00
2021-06-05 21:33:46 +02:00
2021-01-29 15:54:44 +00:00
2021-05-10 13:43:58 +01:00
2019-08-16 13:31:52 +02:00
2021-04-30 11:16:51 +01:00
2021-03-08 17:20:01 +00:00
2021-05-12 17:42:23 +02:00
2020-09-09 09:27:09 -04:00
2020-09-09 09:27:09 -04:00
2019-08-16 13:31:52 +02:00
2020-03-17 12:22:36 -04:00
2020-08-03 17:55:03 +01:00
2020-11-15 17:04:40 +01:00
2021-03-23 11:47:31 +00:00
2020-09-09 09:27:09 -04:00
2020-09-09 09:27:09 -04:00
2020-09-18 14:12:32 -04:00
2020-11-15 17:04:40 +01:00
2021-01-29 15:54:42 +00:00
2021-03-08 17:20:01 +00:00
2020-12-15 12:51:52 -05:00
2019-06-12 13:20:21 +02:00
2020-12-18 15:20:17 -05:00
2020-12-18 15:20:18 -05:00
2021-03-19 15:18:43 +01:00
2020-05-27 11:23:07 -07:00
2020-09-09 09:27:09 -04:00
2020-12-10 12:15:04 -05:00
2020-09-18 14:12:32 -04:00
2021-03-15 17:00:58 +01:00
2020-09-09 09:27:09 -04:00