forked from alwin.berger/FRET-qemu

* remotes/rth/tcg-next: tcg/i386: Use SHLX/SHRX/SARX instructions tcg/i386: Use ANDN instruction tcg/i386: Add tcg_out_vex_modrm tcg/i386: Move TCG_CT_CONST_* to tcg-target.c disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX tcg/optimize: Add more identity simplifications tcg/optimize: Optmize ANDC X,Y,Y to MOV X,0 tcg/optimize: Simply some logical ops to NOT tcg/optimize: Handle known-zeros masks for ANDC tcg/optimize: add known-zero bits compute for load ops tcg/optimize: improve known-zero bits for 32-bit ops tcg/optimize: fix known-zero bits optimization tcg/optimize: fix known-zero bits for right shift ops tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]. TCG: Fix 32-bit host allocation typo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
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