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hw/pci-bridge/cxl_downstream: Set default link width and link speed

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Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2023-10-23 17:07:58 +01:00 committed by Michael S. Tsirkin
parent 3314efd276
commit 314f5033c6
1 changed files with 14 additions and 0 deletions
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14
hw/pci-bridge/cxl_downstream.c
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@ -210,6 +210,19 @@ static void cxl_dsp_exitfn(PCIDevice *d)
pci_bridge_exitfn(d); pci_bridge_exitfn(d);
} }
static void cxl_dsp_instance_post_init(Object *obj)
{
PCIESlot *s = PCIE_SLOT(obj);
if (!s->speed) {
s->speed = QEMU_PCI_EXP_LNK_2_5GT;
}
if (!s->width) {
s->width = QEMU_PCI_EXP_LNK_X1;
}
}
static void cxl_dsp_class_init(ObjectClass *oc, void *data) static void cxl_dsp_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
@ -230,6 +243,7 @@ static const TypeInfo cxl_dsp_info = {
.name = TYPE_CXL_DSP, .name = TYPE_CXL_DSP,
.instance_size = sizeof(CXLDownstreamPort), .instance_size = sizeof(CXLDownstreamPort),
.parent = TYPE_PCIE_SLOT, .parent = TYPE_PCIE_SLOT,
.instance_post_init = cxl_dsp_instance_post_init,
.class_init = cxl_dsp_class_init, .class_init = cxl_dsp_class_init,
.interfaces = (InterfaceInfo[]) { .interfaces = (InterfaceInfo[]) {
{ INTERFACE_PCIE_DEVICE }, { INTERFACE_PCIE_DEVICE },