520 lines
16 KiB
C
520 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016-2017 Micron Technology, Inc.
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*
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* Authors:
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* Peter Pan <peterpandong@micron.com>
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*/
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#ifndef __LINUX_MTD_SPINAND_H
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#define __LINUX_MTD_SPINAND_H
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#include <linux/mutex.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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/**
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* Standard SPI NAND flash operations
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*/
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#define SPINAND_RESET_OP \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_WR_EN_DIS_OP(enable) \
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SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_READID_OP(naddr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
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SPI_MEM_OP_ADDR(naddr, 0, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 1))
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#define SPINAND_SET_FEATURE_OP(reg, valptr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
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SPI_MEM_OP_ADDR(1, reg, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(1, valptr, 1))
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#define SPINAND_GET_FEATURE_OP(reg, valptr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
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SPI_MEM_OP_ADDR(1, reg, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_IN(1, valptr, 1))
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#define SPINAND_BLK_ERASE_OP(addr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_PAGE_READ_OP(addr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 1))
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#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 1))
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#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 2))
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#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 2))
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#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 4))
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#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 4))
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#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
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SPI_MEM_OP_ADDR(2, addr, 2), \
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SPI_MEM_OP_DUMMY(ndummy, 2), \
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SPI_MEM_OP_DATA_IN(len, buf, 2))
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#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
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SPI_MEM_OP_ADDR(3, addr, 2), \
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SPI_MEM_OP_DUMMY(ndummy, 2), \
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SPI_MEM_OP_DATA_IN(len, buf, 2))
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#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
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SPI_MEM_OP_ADDR(2, addr, 4), \
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SPI_MEM_OP_DUMMY(ndummy, 4), \
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SPI_MEM_OP_DATA_IN(len, buf, 4))
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#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
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SPI_MEM_OP_ADDR(3, addr, 4), \
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SPI_MEM_OP_DUMMY(ndummy, 4), \
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SPI_MEM_OP_DATA_IN(len, buf, 4))
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#define SPINAND_PROG_EXEC_OP(addr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_PROG_LOAD(reset, addr, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(len, buf, 1))
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#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(len, buf, 4))
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/**
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* Standard SPI NAND flash commands
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*/
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#define SPINAND_CMD_PROG_LOAD_X4 0x32
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#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
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/* feature register */
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#define REG_BLOCK_LOCK 0xa0
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#define BL_ALL_UNLOCKED 0x00
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/* configuration register */
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#define REG_CFG 0xb0
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#define CFG_OTP_ENABLE BIT(6)
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#define CFG_ECC_ENABLE BIT(4)
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#define CFG_QUAD_ENABLE BIT(0)
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/* status register */
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#define REG_STATUS 0xc0
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#define STATUS_BUSY BIT(0)
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#define STATUS_ERASE_FAILED BIT(2)
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#define STATUS_PROG_FAILED BIT(3)
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#define STATUS_ECC_MASK GENMASK(5, 4)
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#define STATUS_ECC_NO_BITFLIPS (0 << 4)
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#define STATUS_ECC_HAS_BITFLIPS (1 << 4)
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#define STATUS_ECC_UNCOR_ERROR (2 << 4)
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struct spinand_op;
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struct spinand_device;
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#define SPINAND_MAX_ID_LEN 4
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/*
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* For erase, write and read operation, we got the following timings :
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* tBERS (erase) 1ms to 4ms
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* tPROG 300us to 400us
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* tREAD 25us to 100us
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* In order to minimize latency, the min value is divided by 4 for the
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* initial delay, and dividing by 20 for the poll delay.
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* For reset, 5us/10us/500us if the device is respectively
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* reading/programming/erasing when the RESET occurs. Since we always
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* issue a RESET when the device is IDLE, 5us is selected for both initial
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* and poll delay.
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*/
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#define SPINAND_READ_INITIAL_DELAY_US 6
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#define SPINAND_READ_POLL_DELAY_US 5
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#define SPINAND_RESET_INITIAL_DELAY_US 5
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#define SPINAND_RESET_POLL_DELAY_US 5
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#define SPINAND_WRITE_INITIAL_DELAY_US 75
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#define SPINAND_WRITE_POLL_DELAY_US 15
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#define SPINAND_ERASE_INITIAL_DELAY_US 250
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#define SPINAND_ERASE_POLL_DELAY_US 50
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#define SPINAND_WAITRDY_TIMEOUT_MS 400
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/**
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* struct spinand_id - SPI NAND id structure
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* @data: buffer containing the id bytes. Currently 4 bytes large, but can
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* be extended if required
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* @len: ID length
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*/
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struct spinand_id {
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u8 data[SPINAND_MAX_ID_LEN];
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int len;
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};
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enum spinand_readid_method {
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SPINAND_READID_METHOD_OPCODE,
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SPINAND_READID_METHOD_OPCODE_ADDR,
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SPINAND_READID_METHOD_OPCODE_DUMMY,
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};
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/**
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* struct spinand_devid - SPI NAND device id structure
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* @id: device id of current chip
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* @len: number of bytes in device id
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* @method: method to read chip id
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* There are 3 possible variants:
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* SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
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* after read_id opcode.
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* SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
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* read_id opcode + 1-byte address.
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* SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
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* read_id opcode + 1 dummy byte.
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*/
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struct spinand_devid {
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const u8 *id;
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const u8 len;
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const enum spinand_readid_method method;
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};
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/**
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* struct manufacurer_ops - SPI NAND manufacturer specific operations
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* @init: initialize a SPI NAND device
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* @cleanup: cleanup a SPI NAND device
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*
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* Each SPI NAND manufacturer driver should implement this interface so that
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* NAND chips coming from this vendor can be initialized properly.
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*/
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struct spinand_manufacturer_ops {
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int (*init)(struct spinand_device *spinand);
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void (*cleanup)(struct spinand_device *spinand);
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};
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/**
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* struct spinand_manufacturer - SPI NAND manufacturer instance
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* @id: manufacturer ID
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* @name: manufacturer name
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* @devid_len: number of bytes in device ID
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* @chips: supported SPI NANDs under current manufacturer
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* @nchips: number of SPI NANDs available in chips array
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* @ops: manufacturer operations
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*/
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struct spinand_manufacturer {
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u8 id;
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char *name;
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const struct spinand_info *chips;
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const size_t nchips;
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const struct spinand_manufacturer_ops *ops;
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};
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/* SPI NAND manufacturers */
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extern const struct spinand_manufacturer ato_spinand_manufacturer;
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extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
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extern const struct spinand_manufacturer macronix_spinand_manufacturer;
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extern const struct spinand_manufacturer micron_spinand_manufacturer;
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extern const struct spinand_manufacturer paragon_spinand_manufacturer;
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extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
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extern const struct spinand_manufacturer winbond_spinand_manufacturer;
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extern const struct spinand_manufacturer xtx_spinand_manufacturer;
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/**
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* struct spinand_op_variants - SPI NAND operation variants
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* @ops: the list of variants for a given operation
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* @nops: the number of variants
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*
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* Some operations like read-from-cache/write-to-cache have several variants
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* depending on the number of IO lines you use to transfer data or address
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* cycles. This structure is a way to describe the different variants supported
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* by a chip and let the core pick the best one based on the SPI mem controller
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* capabilities.
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*/
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struct spinand_op_variants {
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const struct spi_mem_op *ops;
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unsigned int nops;
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};
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#define SPINAND_OP_VARIANTS(name, ...) \
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const struct spinand_op_variants name = { \
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.ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
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.nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
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sizeof(struct spi_mem_op), \
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}
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/**
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* spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
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* chip
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* @get_status: get the ECC status. Should return a positive number encoding
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* the number of corrected bitflips if correction was possible or
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* -EBADMSG if there are uncorrectable errors. I can also return
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* other negative error codes if the error is not caused by
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* uncorrectable bitflips
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* @ooblayout: the OOB layout used by the on-die ECC implementation
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*/
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struct spinand_ecc_info {
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int (*get_status)(struct spinand_device *spinand, u8 status);
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const struct mtd_ooblayout_ops *ooblayout;
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};
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#define SPINAND_HAS_QE_BIT BIT(0)
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#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
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/**
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* struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
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* @status: status of the last wait operation that will be used in case
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* ->get_status() is not populated by the spinand device.
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*/
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struct spinand_ondie_ecc_conf {
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u8 status;
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};
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/**
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* struct spinand_info - Structure used to describe SPI NAND chips
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* @model: model name
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* @devid: device ID
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* @flags: OR-ing of the SPINAND_XXX flags
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* @memorg: memory organization
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* @eccreq: ECC requirements
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* @eccinfo: on-die ECC info
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* @op_variants: operations variants
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* @op_variants.read_cache: variants of the read-cache operation
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* @op_variants.write_cache: variants of the write-cache operation
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* @op_variants.update_cache: variants of the update-cache operation
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* @select_target: function used to select a target/die. Required only for
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* multi-die chips
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*
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* Each SPI NAND manufacturer driver should have a spinand_info table
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* describing all the chips supported by the driver.
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*/
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struct spinand_info {
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const char *model;
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struct spinand_devid devid;
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u32 flags;
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struct nand_memory_organization memorg;
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struct nand_ecc_props eccreq;
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struct spinand_ecc_info eccinfo;
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struct {
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const struct spinand_op_variants *read_cache;
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const struct spinand_op_variants *write_cache;
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const struct spinand_op_variants *update_cache;
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} op_variants;
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int (*select_target)(struct spinand_device *spinand,
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unsigned int target);
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};
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#define SPINAND_ID(__method, ...) \
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{ \
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.id = (const u8[]){ __VA_ARGS__ }, \
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.len = sizeof((u8[]){ __VA_ARGS__ }), \
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.method = __method, \
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}
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#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
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{ \
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.read_cache = __read, \
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.write_cache = __write, \
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.update_cache = __update, \
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}
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#define SPINAND_ECCINFO(__ooblayout, __get_status) \
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.eccinfo = { \
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.ooblayout = __ooblayout, \
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.get_status = __get_status, \
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}
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#define SPINAND_SELECT_TARGET(__func) \
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.select_target = __func,
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#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
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__flags, ...) \
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{ \
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.model = __model, \
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.devid = __id, \
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.memorg = __memorg, \
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.eccreq = __eccreq, \
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.op_variants = __op_variants, \
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.flags = __flags, \
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__VA_ARGS__ \
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}
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struct spinand_dirmap {
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struct spi_mem_dirmap_desc *wdesc;
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struct spi_mem_dirmap_desc *rdesc;
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struct spi_mem_dirmap_desc *wdesc_ecc;
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struct spi_mem_dirmap_desc *rdesc_ecc;
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};
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/**
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* struct spinand_device - SPI NAND device instance
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* @base: NAND device instance
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* @spimem: pointer to the SPI mem object
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* @lock: lock used to serialize accesses to the NAND
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* @id: NAND ID as returned by READ_ID
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* @flags: NAND flags
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* @op_templates: various SPI mem op templates
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* @op_templates.read_cache: read cache op template
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* @op_templates.write_cache: write cache op template
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* @op_templates.update_cache: update cache op template
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* @select_target: select a specific target/die. Usually called before sending
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* a command addressing a page or an eraseblock embedded in
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* this die. Only required if your chip exposes several dies
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* @cur_target: currently selected target/die
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* @eccinfo: on-die ECC information
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* @cfg_cache: config register cache. One entry per die
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* @databuf: bounce buffer for data
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* @oobbuf: bounce buffer for OOB data
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* @scratchbuf: buffer used for everything but page accesses. This is needed
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* because the spi-mem interface explicitly requests that buffers
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* passed in spi_mem_op be DMA-able, so we can't based the bufs on
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* the stack
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* @manufacturer: SPI NAND manufacturer information
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* @priv: manufacturer private data
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*/
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struct spinand_device {
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struct nand_device base;
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struct spi_mem *spimem;
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struct mutex lock;
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struct spinand_id id;
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u32 flags;
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struct {
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const struct spi_mem_op *read_cache;
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const struct spi_mem_op *write_cache;
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const struct spi_mem_op *update_cache;
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} op_templates;
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struct spinand_dirmap *dirmaps;
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int (*select_target)(struct spinand_device *spinand,
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unsigned int target);
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unsigned int cur_target;
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|
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struct spinand_ecc_info eccinfo;
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|
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u8 *cfg_cache;
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|
u8 *databuf;
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|
u8 *oobbuf;
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|
u8 *scratchbuf;
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|
const struct spinand_manufacturer *manufacturer;
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|
void *priv;
|
|
};
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|
|
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/**
|
|
* mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
|
|
* @mtd: MTD instance
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|
*
|
|
* Return: the SPI NAND device attached to @mtd.
|
|
*/
|
|
static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
|
|
{
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|
return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
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|
}
|
|
|
|
/**
|
|
* spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
|
|
* @spinand: SPI NAND device
|
|
*
|
|
* Return: the MTD device embedded in @spinand.
|
|
*/
|
|
static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
|
|
{
|
|
return nanddev_to_mtd(&spinand->base);
|
|
}
|
|
|
|
/**
|
|
* nand_to_spinand() - Get the SPI NAND device embedding an NAND object
|
|
* @nand: NAND object
|
|
*
|
|
* Return: the SPI NAND device embedding @nand.
|
|
*/
|
|
static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
|
|
{
|
|
return container_of(nand, struct spinand_device, base);
|
|
}
|
|
|
|
/**
|
|
* spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
|
|
* @spinand: SPI NAND device
|
|
*
|
|
* Return: the NAND device embedded in @spinand.
|
|
*/
|
|
static inline struct nand_device *
|
|
spinand_to_nand(struct spinand_device *spinand)
|
|
{
|
|
return &spinand->base;
|
|
}
|
|
|
|
/**
|
|
* spinand_set_of_node - Attach a DT node to a SPI NAND device
|
|
* @spinand: SPI NAND device
|
|
* @np: DT node
|
|
*
|
|
* Attach a DT node to a SPI NAND device.
|
|
*/
|
|
static inline void spinand_set_of_node(struct spinand_device *spinand,
|
|
struct device_node *np)
|
|
{
|
|
nanddev_set_of_node(&spinand->base, np);
|
|
}
|
|
|
|
int spinand_match_and_init(struct spinand_device *spinand,
|
|
const struct spinand_info *table,
|
|
unsigned int table_size,
|
|
enum spinand_readid_method rdid_method);
|
|
|
|
int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
|
|
int spinand_select_target(struct spinand_device *spinand, unsigned int target);
|
|
|
|
#endif /* __LINUX_MTD_SPINAND_H */
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