608 lines
17 KiB
C
608 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HiSilicon Hixxxx UFS Driver
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*
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* Copyright (c) 2016-2017 Linaro Ltd.
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*/
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <ufs/ufshcd.h>
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#include "ufshcd-pltfrm.h"
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#include <ufs/unipro.h>
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#include "ufs-hisi.h"
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#include <ufs/ufshci.h>
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#include <ufs/ufs_quirks.h>
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static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
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{
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int err = 0;
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u32 tx_fsm_val_0 = 0;
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u32 tx_fsm_val_1 = 0;
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unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
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do {
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err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
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&tx_fsm_val_0);
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err |= ufshcd_dme_get(hba,
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UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
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if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
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tx_fsm_val_1 == TX_FSM_HIBERN8))
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break;
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/* sleep for max. 200us */
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usleep_range(100, 200);
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} while (time_before(jiffies, timeout));
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/*
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* we might have scheduled out for long during polling so
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* check the state again.
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*/
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if (time_after(jiffies, timeout)) {
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err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
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&tx_fsm_val_0);
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err |= ufshcd_dme_get(hba,
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UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
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}
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if (err) {
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dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
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__func__, err);
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} else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
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tx_fsm_val_1 != TX_FSM_HIBERN8) {
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err = -1;
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dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
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__func__, tx_fsm_val_0, tx_fsm_val_1);
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}
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return err;
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}
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static void ufs_hisi_clk_init(struct ufs_hba *hba)
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{
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struct ufs_hisi_host *host = ufshcd_get_variant(hba);
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ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
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if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN)
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mdelay(1);
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/* use abb clk */
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ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL);
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ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN);
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/* open mphy ref clk */
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ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
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}
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static void ufs_hisi_soc_init(struct ufs_hba *hba)
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{
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struct ufs_hisi_host *host = ufshcd_get_variant(hba);
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u32 reg;
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if (!IS_ERR(host->rst))
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reset_control_assert(host->rst);
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/* HC_PSW powerup */
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ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL);
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udelay(10);
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/* notify PWR ready */
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ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL);
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ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0,
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UFS_DEVICE_RESET_CTRL);
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reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL);
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reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK;
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/* set cfg clk freq */
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ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL);
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/* set ref clk freq */
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ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL);
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/* bypass ufs clk gate */
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ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS,
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CLOCK_GATE_BYPASS);
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ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL);
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/* open psw clk */
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ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL);
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/* disable ufshc iso */
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ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL);
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/* disable phy iso */
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ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN);
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/* notice iso disable */
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ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL);
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/* disable lp_reset_n */
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ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN);
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mdelay(1);
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ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET,
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UFS_DEVICE_RESET_CTRL);
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msleep(20);
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/*
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* enable the fix of linereset recovery,
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* and enable rx_reset/tx_rest beat
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* enable ref_clk_en override(bit5) &
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* override value = 1(bit4), with mask
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*/
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ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL);
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if (!IS_ERR(host->rst))
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reset_control_deassert(host->rst);
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}
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static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
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{
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struct ufs_hisi_host *host = ufshcd_get_variant(hba);
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int err;
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uint32_t value;
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uint32_t reg;
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/* Unipro VS_mphy_disable */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1);
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/* PA_HSSeries */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2);
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/* MPHY CBRATESEL */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1);
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/* MPHY CBOVRCTRL2 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
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/* MPHY CBOVRCTRL3 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
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if (host->caps & UFS_HISI_CAP_PHY10nm) {
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/* MPHY CBOVRCTRL4 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
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/* MPHY CBOVRCTRL5 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
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}
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/* Unipro VS_MphyCfgUpdt */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
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/* MPHY RXOVRCTRL4 rx0 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58);
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/* MPHY RXOVRCTRL4 rx1 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58);
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/* MPHY RXOVRCTRL5 rx0 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB);
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/* MPHY RXOVRCTRL5 rx1 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB);
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/* MPHY RXSQCONTROL rx0 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1);
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/* MPHY RXSQCONTROL rx1 */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1);
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/* Unipro VS_MphyCfgUpdt */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
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if (host->caps & UFS_HISI_CAP_PHY10nm) {
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/* RX_Hibern8Time_Capability*/
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
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/* RX_Hibern8Time_Capability*/
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
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/* RX_Min_ActivateTime */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
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/* RX_Min_ActivateTime*/
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
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} else {
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/* Tactive RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
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/* Tactive RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
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}
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/* Gear3 Synclength */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
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/* Gear3 Synclength */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F);
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/* Gear2 Synclength */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F);
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/* Gear2 Synclength */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F);
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/* Gear1 Synclength */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F);
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/* Gear1 Synclength */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F);
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/* Thibernate Tx */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5);
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/* Thibernate Tx */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
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/* Unipro VS_mphy_disable */
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ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value);
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if (value != 0x1)
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dev_info(hba->dev,
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"Warring!!! Unipro VS_mphy_disable is 0x%x\n", value);
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/* Unipro VS_mphy_disable */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
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err = ufs_hisi_check_hibern8(hba);
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if (err)
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dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
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if (!(host->caps & UFS_HISI_CAP_PHY10nm))
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ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
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/* disable auto H8 */
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reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
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reg = reg & (~UFS_AHIT_AH8ITV_MASK);
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ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
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/* Unipro PA_Local_TX_LCC_Enable */
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ufshcd_disable_host_tx_lcc(hba);
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/* close Unipro VS_Mk2ExtnSupport */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0);
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ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value);
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if (value != 0) {
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/* Ensure close success */
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dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n");
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}
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return err;
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}
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static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
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{
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struct ufs_hisi_host *host = ufshcd_get_variant(hba);
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/* Unipro DL_AFC0CreditThreshold */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0);
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/* Unipro DL_TC0OutAckThreshold */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0);
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/* Unipro DL_TC0TXFCThreshold */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9);
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/* not bypass ufs clk gate */
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ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS,
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CLOCK_GATE_BYPASS);
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ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS,
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UFS_SYSCTRL);
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/* select received symbol cnt */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000);
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/* reset counter0 and enable */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005);
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return 0;
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}
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static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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switch (status) {
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case PRE_CHANGE:
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err = ufs_hisi_link_startup_pre_change(hba);
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break;
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case POST_CHANGE:
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err = ufs_hisi_link_startup_post_change(hba);
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break;
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default:
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break;
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}
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return err;
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}
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static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
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{
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ufshcd_init_pwr_dev_param(hisi_param);
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}
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static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
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{
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struct ufs_hisi_host *host = ufshcd_get_variant(hba);
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if (host->caps & UFS_HISI_CAP_PHY10nm) {
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/*
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* Boston platform need to set SaveConfigTime to 0x13,
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* and change sync length to maximum value
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*/
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/* VS_DebugSaveConfigTime */
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ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
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/* g1 sync length */
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ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
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/* g2 sync length */
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ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
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/* g3 sync length */
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ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
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/* PA_Hibern8Time */
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ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
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/* PA_Tactivate */
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ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
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}
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if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
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pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
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/* VS_DebugSaveConfigTime */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10);
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/* sync length */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48);
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}
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/* update */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1);
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/* PA_TxSkip */
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0);
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/*PA_PWRModeUserData0 = 8191, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191);
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/*PA_PWRModeUserData1 = 65535, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535);
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/*PA_PWRModeUserData2 = 32767, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767);
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/*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191);
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/*DME_TC0ReplayTimeOutVal = 65535, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535);
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/*DME_AFC0ReqTimeOutVal = 32767, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767);
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/*PA_PWRModeUserData3 = 8191, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191);
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/*PA_PWRModeUserData4 = 65535, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535);
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/*PA_PWRModeUserData5 = 32767, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767);
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/*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191);
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/*DME_TC1ReplayTimeOutVal = 65535, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535);
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/*DME_AFC1ReqTimeOutVal = 32767, default is 0*/
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ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
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}
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static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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struct ufs_dev_params ufs_hisi_cap;
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int ret = 0;
|
|
|
|
if (!dev_req_params) {
|
|
dev_err(hba->dev,
|
|
"%s: incoming dev_req_params is NULL\n", __func__);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
switch (status) {
|
|
case PRE_CHANGE:
|
|
ufs_hisi_set_dev_cap(&ufs_hisi_cap);
|
|
ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
|
|
dev_max_params, dev_req_params);
|
|
if (ret) {
|
|
dev_err(hba->dev,
|
|
"%s: failed to determine capabilities\n", __func__);
|
|
goto out;
|
|
}
|
|
|
|
ufs_hisi_pwr_change_pre_change(hba);
|
|
break;
|
|
case POST_CHANGE:
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int ufs_hisi_suspend_prepare(struct device *dev)
|
|
{
|
|
/* RPM and SPM are different. Refer ufs_hisi_suspend() */
|
|
return __ufshcd_suspend_prepare(dev, false);
|
|
}
|
|
|
|
static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
|
|
enum ufs_notify_change_status status)
|
|
{
|
|
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
|
|
|
|
if (status == PRE_CHANGE)
|
|
return 0;
|
|
|
|
if (pm_op == UFS_RUNTIME_PM)
|
|
return 0;
|
|
|
|
if (host->in_suspend) {
|
|
WARN_ON(1);
|
|
return 0;
|
|
}
|
|
|
|
ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
|
|
udelay(10);
|
|
/* set ref_dig_clk override of PHY PCS to 0 */
|
|
ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL);
|
|
|
|
host->in_suspend = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
|
|
{
|
|
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
|
|
|
|
if (!host->in_suspend)
|
|
return 0;
|
|
|
|
/* set ref_dig_clk override of PHY PCS to 1 */
|
|
ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL);
|
|
udelay(10);
|
|
ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
|
|
|
|
host->in_suspend = false;
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_hisi_get_resource(struct ufs_hisi_host *host)
|
|
{
|
|
struct device *dev = host->hba->dev;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
/* get resource of ufs sys ctrl */
|
|
host->ufs_sys_ctrl = devm_platform_ioremap_resource(pdev, 1);
|
|
return PTR_ERR_OR_ZERO(host->ufs_sys_ctrl);
|
|
}
|
|
|
|
static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba)
|
|
{
|
|
hba->rpm_lvl = UFS_PM_LVL_1;
|
|
hba->spm_lvl = UFS_PM_LVL_3;
|
|
}
|
|
|
|
/**
|
|
* ufs_hisi_init_common
|
|
* @hba: host controller instance
|
|
*/
|
|
static int ufs_hisi_init_common(struct ufs_hba *hba)
|
|
{
|
|
int err = 0;
|
|
struct device *dev = hba->dev;
|
|
struct ufs_hisi_host *host;
|
|
|
|
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
host->hba = hba;
|
|
ufshcd_set_variant(hba, host);
|
|
|
|
host->rst = devm_reset_control_get(dev, "rst");
|
|
if (IS_ERR(host->rst)) {
|
|
dev_err(dev, "%s: failed to get reset control\n", __func__);
|
|
err = PTR_ERR(host->rst);
|
|
goto error;
|
|
}
|
|
|
|
ufs_hisi_set_pm_lvl(hba);
|
|
|
|
err = ufs_hisi_get_resource(host);
|
|
if (err)
|
|
goto error;
|
|
|
|
return 0;
|
|
|
|
error:
|
|
ufshcd_set_variant(hba, NULL);
|
|
return err;
|
|
}
|
|
|
|
static int ufs_hi3660_init(struct ufs_hba *hba)
|
|
{
|
|
int ret = 0;
|
|
struct device *dev = hba->dev;
|
|
|
|
ret = ufs_hisi_init_common(hba);
|
|
if (ret) {
|
|
dev_err(dev, "%s: ufs common init fail\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
ufs_hisi_clk_init(hba);
|
|
|
|
ufs_hisi_soc_init(hba);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_hi3670_init(struct ufs_hba *hba)
|
|
{
|
|
int ret = 0;
|
|
struct device *dev = hba->dev;
|
|
struct ufs_hisi_host *host;
|
|
|
|
ret = ufs_hisi_init_common(hba);
|
|
if (ret) {
|
|
dev_err(dev, "%s: ufs common init fail\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
ufs_hisi_clk_init(hba);
|
|
|
|
ufs_hisi_soc_init(hba);
|
|
|
|
/* Add cap for 10nm PHY variant on HI3670 SoC */
|
|
host = ufshcd_get_variant(hba);
|
|
host->caps |= UFS_HISI_CAP_PHY10nm;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
|
|
.name = "hi3660",
|
|
.init = ufs_hi3660_init,
|
|
.link_startup_notify = ufs_hisi_link_startup_notify,
|
|
.pwr_change_notify = ufs_hisi_pwr_change_notify,
|
|
.suspend = ufs_hisi_suspend,
|
|
.resume = ufs_hisi_resume,
|
|
};
|
|
|
|
static const struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
|
|
.name = "hi3670",
|
|
.init = ufs_hi3670_init,
|
|
.link_startup_notify = ufs_hisi_link_startup_notify,
|
|
.pwr_change_notify = ufs_hisi_pwr_change_notify,
|
|
.suspend = ufs_hisi_suspend,
|
|
.resume = ufs_hisi_resume,
|
|
};
|
|
|
|
static const struct of_device_id ufs_hisi_of_match[] = {
|
|
{ .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
|
|
{ .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
|
|
|
|
static int ufs_hisi_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id;
|
|
|
|
of_id = of_match_node(ufs_hisi_of_match, pdev->dev.of_node);
|
|
|
|
return ufshcd_pltfrm_init(pdev, of_id->data);
|
|
}
|
|
|
|
static int ufs_hisi_remove(struct platform_device *pdev)
|
|
{
|
|
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
|
|
|
ufshcd_remove(hba);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops ufs_hisi_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
|
|
SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
|
|
.prepare = ufs_hisi_suspend_prepare,
|
|
.complete = ufshcd_resume_complete,
|
|
};
|
|
|
|
static struct platform_driver ufs_hisi_pltform = {
|
|
.probe = ufs_hisi_probe,
|
|
.remove = ufs_hisi_remove,
|
|
.shutdown = ufshcd_pltfrm_shutdown,
|
|
.driver = {
|
|
.name = "ufshcd-hisi",
|
|
.pm = &ufs_hisi_pm_ops,
|
|
.of_match_table = of_match_ptr(ufs_hisi_of_match),
|
|
},
|
|
};
|
|
module_platform_driver(ufs_hisi_pltform);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:ufshcd-hisi");
|
|
MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver");
|