635 lines
14 KiB
C
635 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright (c) 2021, Microsoft Corporation. */
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#ifndef _MANA_H
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#define _MANA_H
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#include "gdma.h"
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#include "hw_channel.h"
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/* Microsoft Azure Network Adapter (MANA)'s definitions
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*
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* Structures labeled with "HW DATA" are exchanged with the hardware. All of
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* them are naturally aligned and hence don't need __packed.
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*/
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/* MANA protocol version */
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#define MANA_MAJOR_VERSION 0
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#define MANA_MINOR_VERSION 1
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#define MANA_MICRO_VERSION 1
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typedef u64 mana_handle_t;
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#define INVALID_MANA_HANDLE ((mana_handle_t)-1)
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enum TRI_STATE {
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TRI_STATE_UNKNOWN = -1,
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TRI_STATE_FALSE = 0,
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TRI_STATE_TRUE = 1
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};
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/* Number of entries for hardware indirection table must be in power of 2 */
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#define MANA_INDIRECT_TABLE_SIZE 64
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#define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1)
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/* The Toeplitz hash key's length in bytes: should be multiple of 8 */
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#define MANA_HASH_KEY_SIZE 40
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#define COMP_ENTRY_SIZE 64
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#define ADAPTER_MTU_SIZE 1500
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#define MAX_FRAME_SIZE (ADAPTER_MTU_SIZE + 14)
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#define RX_BUFFERS_PER_QUEUE 512
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#define MAX_SEND_BUFFERS_PER_QUEUE 256
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#define EQ_SIZE (8 * PAGE_SIZE)
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#define LOG2_EQ_THROTTLE 3
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#define MAX_PORTS_IN_MANA_DEV 256
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struct mana_stats_rx {
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u64 packets;
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u64 bytes;
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u64 xdp_drop;
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u64 xdp_tx;
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u64 xdp_redirect;
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struct u64_stats_sync syncp;
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};
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struct mana_stats_tx {
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u64 packets;
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u64 bytes;
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u64 xdp_xmit;
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struct u64_stats_sync syncp;
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};
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struct mana_txq {
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struct gdma_queue *gdma_sq;
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union {
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u32 gdma_txq_id;
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struct {
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u32 reserved1 : 10;
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u32 vsq_frame : 14;
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u32 reserved2 : 8;
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};
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};
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u16 vp_offset;
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struct net_device *ndev;
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/* The SKBs are sent to the HW and we are waiting for the CQEs. */
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struct sk_buff_head pending_skbs;
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struct netdev_queue *net_txq;
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atomic_t pending_sends;
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struct mana_stats_tx stats;
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};
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/* skb data and frags dma mappings */
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struct mana_skb_head {
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dma_addr_t dma_handle[MAX_SKB_FRAGS + 1];
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u32 size[MAX_SKB_FRAGS + 1];
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};
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#define MANA_HEADROOM sizeof(struct mana_skb_head)
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enum mana_tx_pkt_format {
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MANA_SHORT_PKT_FMT = 0,
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MANA_LONG_PKT_FMT = 1,
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};
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struct mana_tx_short_oob {
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u32 pkt_fmt : 2;
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u32 is_outer_ipv4 : 1;
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u32 is_outer_ipv6 : 1;
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u32 comp_iphdr_csum : 1;
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u32 comp_tcp_csum : 1;
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u32 comp_udp_csum : 1;
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u32 supress_txcqe_gen : 1;
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u32 vcq_num : 24;
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u32 trans_off : 10; /* Transport header offset */
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u32 vsq_frame : 14;
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u32 short_vp_offset : 8;
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}; /* HW DATA */
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struct mana_tx_long_oob {
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u32 is_encap : 1;
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u32 inner_is_ipv6 : 1;
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u32 inner_tcp_opt : 1;
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u32 inject_vlan_pri_tag : 1;
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u32 reserved1 : 12;
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u32 pcp : 3; /* 802.1Q */
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u32 dei : 1; /* 802.1Q */
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u32 vlan_id : 12; /* 802.1Q */
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u32 inner_frame_offset : 10;
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u32 inner_ip_rel_offset : 6;
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u32 long_vp_offset : 12;
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u32 reserved2 : 4;
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u32 reserved3;
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u32 reserved4;
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}; /* HW DATA */
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struct mana_tx_oob {
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struct mana_tx_short_oob s_oob;
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struct mana_tx_long_oob l_oob;
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}; /* HW DATA */
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enum mana_cq_type {
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MANA_CQ_TYPE_RX,
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MANA_CQ_TYPE_TX,
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};
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enum mana_cqe_type {
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CQE_INVALID = 0,
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CQE_RX_OKAY = 1,
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CQE_RX_COALESCED_4 = 2,
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CQE_RX_OBJECT_FENCE = 3,
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CQE_RX_TRUNCATED = 4,
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CQE_TX_OKAY = 32,
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CQE_TX_SA_DROP = 33,
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CQE_TX_MTU_DROP = 34,
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CQE_TX_INVALID_OOB = 35,
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CQE_TX_INVALID_ETH_TYPE = 36,
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CQE_TX_HDR_PROCESSING_ERROR = 37,
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CQE_TX_VF_DISABLED = 38,
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CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39,
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CQE_TX_VPORT_DISABLED = 40,
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CQE_TX_VLAN_TAGGING_VIOLATION = 41,
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};
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#define MANA_CQE_COMPLETION 1
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struct mana_cqe_header {
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u32 cqe_type : 6;
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u32 client_type : 2;
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u32 vendor_err : 24;
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}; /* HW DATA */
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/* NDIS HASH Types */
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#define NDIS_HASH_IPV4 BIT(0)
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#define NDIS_HASH_TCP_IPV4 BIT(1)
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#define NDIS_HASH_UDP_IPV4 BIT(2)
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#define NDIS_HASH_IPV6 BIT(3)
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#define NDIS_HASH_TCP_IPV6 BIT(4)
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#define NDIS_HASH_UDP_IPV6 BIT(5)
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#define NDIS_HASH_IPV6_EX BIT(6)
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#define NDIS_HASH_TCP_IPV6_EX BIT(7)
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#define NDIS_HASH_UDP_IPV6_EX BIT(8)
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#define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX)
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#define MANA_HASH_L4 \
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(NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \
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NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX)
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struct mana_rxcomp_perpkt_info {
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u32 pkt_len : 16;
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u32 reserved1 : 16;
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u32 reserved2;
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u32 pkt_hash;
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}; /* HW DATA */
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#define MANA_RXCOMP_OOB_NUM_PPI 4
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/* Receive completion OOB */
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struct mana_rxcomp_oob {
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struct mana_cqe_header cqe_hdr;
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u32 rx_vlan_id : 12;
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u32 rx_vlantag_present : 1;
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u32 rx_outer_iphdr_csum_succeed : 1;
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u32 rx_outer_iphdr_csum_fail : 1;
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u32 reserved1 : 1;
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u32 rx_hashtype : 9;
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u32 rx_iphdr_csum_succeed : 1;
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u32 rx_iphdr_csum_fail : 1;
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u32 rx_tcp_csum_succeed : 1;
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u32 rx_tcp_csum_fail : 1;
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u32 rx_udp_csum_succeed : 1;
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u32 rx_udp_csum_fail : 1;
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u32 reserved2 : 1;
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struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI];
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u32 rx_wqe_offset;
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}; /* HW DATA */
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struct mana_tx_comp_oob {
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struct mana_cqe_header cqe_hdr;
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u32 tx_data_offset;
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u32 tx_sgl_offset : 5;
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u32 tx_wqe_offset : 27;
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u32 reserved[12];
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}; /* HW DATA */
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struct mana_rxq;
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#define CQE_POLLING_BUFFER 512
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struct mana_cq {
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struct gdma_queue *gdma_cq;
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/* Cache the CQ id (used to verify if each CQE comes to the right CQ. */
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u32 gdma_id;
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/* Type of the CQ: TX or RX */
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enum mana_cq_type type;
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/* Pointer to the mana_rxq that is pushing RX CQEs to the queue.
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* Only and must be non-NULL if type is MANA_CQ_TYPE_RX.
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*/
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struct mana_rxq *rxq;
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/* Pointer to the mana_txq that is pushing TX CQEs to the queue.
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* Only and must be non-NULL if type is MANA_CQ_TYPE_TX.
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*/
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struct mana_txq *txq;
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/* Buffer which the CQ handler can copy the CQE's into. */
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struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER];
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/* NAPI data */
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struct napi_struct napi;
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int work_done;
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int budget;
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};
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#define GDMA_MAX_RQE_SGES 15
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struct mana_recv_buf_oob {
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/* A valid GDMA work request representing the data buffer. */
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struct gdma_wqe_request wqe_req;
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void *buf_va;
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dma_addr_t buf_dma_addr;
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/* SGL of the buffer going to be sent has part of the work request. */
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u32 num_sge;
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struct gdma_sge sgl[GDMA_MAX_RQE_SGES];
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/* Required to store the result of mana_gd_post_work_request.
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* gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the
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* work queue when the WQE is consumed.
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*/
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struct gdma_posted_wqe_info wqe_inf;
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};
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struct mana_rxq {
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struct gdma_queue *gdma_rq;
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/* Cache the gdma receive queue id */
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u32 gdma_id;
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/* Index of RQ in the vPort, not gdma receive queue id */
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u32 rxq_idx;
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u32 datasize;
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mana_handle_t rxobj;
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struct mana_cq rx_cq;
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struct completion fence_event;
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struct net_device *ndev;
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/* Total number of receive buffers to be allocated */
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u32 num_rx_buf;
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u32 buf_index;
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struct mana_stats_rx stats;
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struct bpf_prog __rcu *bpf_prog;
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struct xdp_rxq_info xdp_rxq;
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struct page *xdp_save_page;
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bool xdp_flush;
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int xdp_rc; /* XDP redirect return code */
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/* MUST BE THE LAST MEMBER:
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* Each receive buffer has an associated mana_recv_buf_oob.
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*/
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struct mana_recv_buf_oob rx_oobs[];
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};
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struct mana_tx_qp {
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struct mana_txq txq;
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struct mana_cq tx_cq;
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mana_handle_t tx_object;
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};
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struct mana_ethtool_stats {
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u64 stop_queue;
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u64 wake_queue;
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};
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struct mana_context {
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struct gdma_dev *gdma_dev;
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u16 num_ports;
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struct mana_eq *eqs;
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struct net_device *ports[MAX_PORTS_IN_MANA_DEV];
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};
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struct mana_port_context {
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struct mana_context *ac;
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struct net_device *ndev;
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u8 mac_addr[ETH_ALEN];
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enum TRI_STATE rss_state;
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mana_handle_t default_rxobj;
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bool tx_shortform_allowed;
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u16 tx_vp_offset;
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struct mana_tx_qp *tx_qp;
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/* Indirection Table for RX & TX. The values are queue indexes */
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u32 indir_table[MANA_INDIRECT_TABLE_SIZE];
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/* Indirection table containing RxObject Handles */
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mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE];
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/* Hash key used by the NIC */
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u8 hashkey[MANA_HASH_KEY_SIZE];
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/* This points to an array of num_queues of RQ pointers. */
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struct mana_rxq **rxqs;
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struct bpf_prog *bpf_prog;
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/* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */
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unsigned int max_queues;
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unsigned int num_queues;
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mana_handle_t port_handle;
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mana_handle_t pf_filter_handle;
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u16 port_idx;
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bool port_is_up;
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bool port_st_save; /* Saved port state */
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struct mana_ethtool_stats eth_stats;
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};
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int mana_start_xmit(struct sk_buff *skb, struct net_device *ndev);
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int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx,
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bool update_hash, bool update_tab);
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int mana_alloc_queues(struct net_device *ndev);
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int mana_attach(struct net_device *ndev);
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int mana_detach(struct net_device *ndev, bool from_close);
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int mana_probe(struct gdma_dev *gd, bool resuming);
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void mana_remove(struct gdma_dev *gd, bool suspending);
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void mana_xdp_tx(struct sk_buff *skb, struct net_device *ndev);
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int mana_xdp_xmit(struct net_device *ndev, int n, struct xdp_frame **frames,
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u32 flags);
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u32 mana_run_xdp(struct net_device *ndev, struct mana_rxq *rxq,
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struct xdp_buff *xdp, void *buf_va, uint pkt_len);
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struct bpf_prog *mana_xdp_get(struct mana_port_context *apc);
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void mana_chn_setxdp(struct mana_port_context *apc, struct bpf_prog *prog);
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int mana_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
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extern const struct ethtool_ops mana_ethtool_ops;
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struct mana_obj_spec {
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u32 queue_index;
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u64 gdma_region;
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u32 queue_size;
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u32 attached_eq;
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u32 modr_ctx_id;
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};
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enum mana_command_code {
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MANA_QUERY_DEV_CONFIG = 0x20001,
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MANA_QUERY_GF_STAT = 0x20002,
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MANA_CONFIG_VPORT_TX = 0x20003,
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MANA_CREATE_WQ_OBJ = 0x20004,
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MANA_DESTROY_WQ_OBJ = 0x20005,
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MANA_FENCE_RQ = 0x20006,
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MANA_CONFIG_VPORT_RX = 0x20007,
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MANA_QUERY_VPORT_CONFIG = 0x20008,
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/* Privileged commands for the PF mode */
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MANA_REGISTER_FILTER = 0x28000,
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MANA_DEREGISTER_FILTER = 0x28001,
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MANA_REGISTER_HW_PORT = 0x28003,
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MANA_DEREGISTER_HW_PORT = 0x28004,
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};
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/* Query Device Configuration */
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struct mana_query_device_cfg_req {
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struct gdma_req_hdr hdr;
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/* MANA Nic Driver Capability flags */
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u64 mn_drv_cap_flags1;
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u64 mn_drv_cap_flags2;
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u64 mn_drv_cap_flags3;
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u64 mn_drv_cap_flags4;
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u32 proto_major_ver;
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u32 proto_minor_ver;
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u32 proto_micro_ver;
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u32 reserved;
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}; /* HW DATA */
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struct mana_query_device_cfg_resp {
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struct gdma_resp_hdr hdr;
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u64 pf_cap_flags1;
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u64 pf_cap_flags2;
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u64 pf_cap_flags3;
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u64 pf_cap_flags4;
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u16 max_num_vports;
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u16 reserved;
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u32 max_num_eqs;
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}; /* HW DATA */
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/* Query vPort Configuration */
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struct mana_query_vport_cfg_req {
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struct gdma_req_hdr hdr;
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u32 vport_index;
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}; /* HW DATA */
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struct mana_query_vport_cfg_resp {
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struct gdma_resp_hdr hdr;
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u32 max_num_sq;
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u32 max_num_rq;
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u32 num_indirection_ent;
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u32 reserved1;
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u8 mac_addr[6];
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u8 reserved2[2];
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mana_handle_t vport;
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}; /* HW DATA */
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/* Configure vPort */
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struct mana_config_vport_req {
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struct gdma_req_hdr hdr;
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mana_handle_t vport;
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u32 pdid;
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u32 doorbell_pageid;
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}; /* HW DATA */
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struct mana_config_vport_resp {
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struct gdma_resp_hdr hdr;
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u16 tx_vport_offset;
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u8 short_form_allowed;
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u8 reserved;
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}; /* HW DATA */
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/* Create WQ Object */
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struct mana_create_wqobj_req {
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struct gdma_req_hdr hdr;
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mana_handle_t vport;
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u32 wq_type;
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u32 reserved;
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u64 wq_gdma_region;
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u64 cq_gdma_region;
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u32 wq_size;
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u32 cq_size;
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u32 cq_moderation_ctx_id;
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u32 cq_parent_qid;
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}; /* HW DATA */
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struct mana_create_wqobj_resp {
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struct gdma_resp_hdr hdr;
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u32 wq_id;
|
|
u32 cq_id;
|
|
mana_handle_t wq_obj;
|
|
}; /* HW DATA */
|
|
|
|
/* Destroy WQ Object */
|
|
struct mana_destroy_wqobj_req {
|
|
struct gdma_req_hdr hdr;
|
|
u32 wq_type;
|
|
u32 reserved;
|
|
mana_handle_t wq_obj_handle;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_destroy_wqobj_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
/* Fence RQ */
|
|
struct mana_fence_rq_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t wq_obj_handle;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_fence_rq_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
/* Configure vPort Rx Steering */
|
|
struct mana_cfg_rx_steer_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t vport;
|
|
u16 num_indir_entries;
|
|
u16 indir_tab_offset;
|
|
u32 rx_enable;
|
|
u32 rss_enable;
|
|
u8 update_default_rxobj;
|
|
u8 update_hashkey;
|
|
u8 update_indir_tab;
|
|
u8 reserved;
|
|
mana_handle_t default_rxobj;
|
|
u8 hashkey[MANA_HASH_KEY_SIZE];
|
|
}; /* HW DATA */
|
|
|
|
struct mana_cfg_rx_steer_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
/* Register HW vPort */
|
|
struct mana_register_hw_vport_req {
|
|
struct gdma_req_hdr hdr;
|
|
u16 attached_gfid;
|
|
u8 is_pf_default_vport;
|
|
u8 reserved1;
|
|
u8 allow_all_ether_types;
|
|
u8 reserved2;
|
|
u8 reserved3;
|
|
u8 reserved4;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_register_hw_vport_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
mana_handle_t hw_vport_handle;
|
|
}; /* HW DATA */
|
|
|
|
/* Deregister HW vPort */
|
|
struct mana_deregister_hw_vport_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t hw_vport_handle;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_deregister_hw_vport_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
/* Register filter */
|
|
struct mana_register_filter_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t vport;
|
|
u8 mac_addr[6];
|
|
u8 reserved1;
|
|
u8 reserved2;
|
|
u8 reserved3;
|
|
u8 reserved4;
|
|
u16 reserved5;
|
|
u32 reserved6;
|
|
u32 reserved7;
|
|
u32 reserved8;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_register_filter_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
mana_handle_t filter_handle;
|
|
}; /* HW DATA */
|
|
|
|
/* Deregister filter */
|
|
struct mana_deregister_filter_req {
|
|
struct gdma_req_hdr hdr;
|
|
mana_handle_t filter_handle;
|
|
}; /* HW DATA */
|
|
|
|
struct mana_deregister_filter_resp {
|
|
struct gdma_resp_hdr hdr;
|
|
}; /* HW DATA */
|
|
|
|
#define MANA_MAX_NUM_QUEUES 64
|
|
|
|
#define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1)
|
|
|
|
struct mana_tx_package {
|
|
struct gdma_wqe_request wqe_req;
|
|
struct gdma_sge sgl_array[5];
|
|
struct gdma_sge *sgl_ptr;
|
|
|
|
struct mana_tx_oob tx_oob;
|
|
|
|
struct gdma_posted_wqe_info wqe_info;
|
|
};
|
|
|
|
#endif /* _MANA_H */
|