324 lines
8.5 KiB
C
324 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*/
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#include "sparx5_main_regs.h"
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#include "sparx5_main.h"
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#include "sparx5_port.h"
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#include "sparx5_tc.h"
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/* The IFH bit position of the first VSTAX bit. This is because the
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* VSTAX bit positions in Data sheet is starting from zero.
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*/
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#define VSTAX 73
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#define ifh_encode_bitfield(ifh, value, pos, _width) \
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({ \
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u32 width = (_width); \
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\
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/* Max width is 5 bytes - 40 bits. In worst case this will
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* spread over 6 bytes - 48 bits
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*/ \
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compiletime_assert(width <= 40, \
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"Unsupported width, must be <= 40"); \
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__ifh_encode_bitfield((ifh), (value), (pos), width); \
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})
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static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
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{
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u8 *ifh_hdr = ifh;
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/* Calculate the Start IFH byte position of this IFH bit position */
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u32 byte = (35 - (pos / 8));
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/* Calculate the Start bit position in the Start IFH byte */
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u32 bit = (pos % 8);
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u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit);
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/* The b0-b7 goes into the start IFH byte */
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if (encode & 0xFF)
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ifh_hdr[byte] |= (u8)((encode & 0xFF));
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/* The b8-b15 goes into the next IFH byte */
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if (encode & 0xFF00)
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ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8);
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/* The b16-b23 goes into the next IFH byte */
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if (encode & 0xFF0000)
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ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16);
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/* The b24-b31 goes into the next IFH byte */
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if (encode & 0xFF000000)
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ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24);
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/* The b32-b39 goes into the next IFH byte */
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if (encode & 0xFF00000000)
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ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32);
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/* The b40-b47 goes into the next IFH byte */
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if (encode & 0xFF0000000000)
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ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40);
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}
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void sparx5_set_port_ifh(void *ifh_hdr, u16 portno)
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{
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/* VSTAX.RSV = 1. MSBit must be 1 */
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ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1);
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/* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */
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ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 55, 1);
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/* MISC.CPU_MASK/DPORT = Destination port */
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ifh_encode_bitfield(ifh_hdr, portno, 29, 8);
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/* MISC.PIPELINE_PT */
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ifh_encode_bitfield(ifh_hdr, 16, 37, 5);
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/* MISC.PIPELINE_ACT */
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ifh_encode_bitfield(ifh_hdr, 1, 42, 3);
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/* FWD.SRC_PORT = CPU */
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ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7);
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/* FWD.SFLOW_ID (disable SFlow sampling) */
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ifh_encode_bitfield(ifh_hdr, 124, 57, 7);
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/* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */
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ifh_encode_bitfield(ifh_hdr, 1, 67, 1);
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}
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void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op)
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{
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ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10);
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}
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void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type)
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{
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ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4);
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}
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void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset)
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{
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ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6);
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}
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void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp)
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{
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ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40);
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}
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static int sparx5_port_open(struct net_device *ndev)
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{
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struct sparx5_port *port = netdev_priv(ndev);
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int err = 0;
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sparx5_port_enable(port, true);
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err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
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if (err) {
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netdev_err(ndev, "Could not attach to PHY\n");
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goto err_connect;
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}
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phylink_start(port->phylink);
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if (!ndev->phydev) {
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/* power up serdes */
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port->conf.power_down = false;
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if (port->conf.serdes_reset)
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err = sparx5_serdes_set(port->sparx5, port, &port->conf);
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else
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err = phy_power_on(port->serdes);
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if (err) {
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netdev_err(ndev, "%s failed\n", __func__);
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goto out_power;
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}
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}
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return 0;
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out_power:
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phylink_stop(port->phylink);
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phylink_disconnect_phy(port->phylink);
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err_connect:
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sparx5_port_enable(port, false);
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return err;
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}
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static int sparx5_port_stop(struct net_device *ndev)
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{
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struct sparx5_port *port = netdev_priv(ndev);
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int err = 0;
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sparx5_port_enable(port, false);
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phylink_stop(port->phylink);
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phylink_disconnect_phy(port->phylink);
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if (!ndev->phydev) {
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/* power down serdes */
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port->conf.power_down = true;
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if (port->conf.serdes_reset)
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err = sparx5_serdes_set(port->sparx5, port, &port->conf);
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else
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err = phy_power_off(port->serdes);
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if (err)
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netdev_err(ndev, "%s failed\n", __func__);
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}
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return 0;
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}
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static void sparx5_set_rx_mode(struct net_device *dev)
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{
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struct sparx5_port *port = netdev_priv(dev);
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struct sparx5 *sparx5 = port->sparx5;
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if (!test_bit(port->portno, sparx5->bridge_mask))
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__dev_mc_sync(dev, sparx5_mc_sync, sparx5_mc_unsync);
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}
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static int sparx5_port_get_phys_port_name(struct net_device *dev,
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char *buf, size_t len)
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{
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struct sparx5_port *port = netdev_priv(dev);
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int ret;
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ret = snprintf(buf, len, "p%d", port->portno);
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if (ret >= len)
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return -EINVAL;
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return 0;
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}
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static int sparx5_set_mac_address(struct net_device *dev, void *p)
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{
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struct sparx5_port *port = netdev_priv(dev);
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struct sparx5 *sparx5 = port->sparx5;
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const struct sockaddr *addr = p;
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if (!is_valid_ether_addr(addr->sa_data))
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return -EADDRNOTAVAIL;
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/* Remove current */
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sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid);
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/* Add new */
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sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid);
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/* Record the address */
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eth_hw_addr_set(dev, addr->sa_data);
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return 0;
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}
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static int sparx5_get_port_parent_id(struct net_device *dev,
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struct netdev_phys_item_id *ppid)
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{
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struct sparx5_port *sparx5_port = netdev_priv(dev);
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struct sparx5 *sparx5 = sparx5_port->sparx5;
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ppid->id_len = sizeof(sparx5->base_mac);
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memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len);
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return 0;
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}
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static int sparx5_port_ioctl(struct net_device *dev, struct ifreq *ifr,
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int cmd)
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{
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struct sparx5_port *sparx5_port = netdev_priv(dev);
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struct sparx5 *sparx5 = sparx5_port->sparx5;
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if (!phy_has_hwtstamp(dev->phydev) && sparx5->ptp) {
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switch (cmd) {
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case SIOCSHWTSTAMP:
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return sparx5_ptp_hwtstamp_set(sparx5_port, ifr);
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case SIOCGHWTSTAMP:
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return sparx5_ptp_hwtstamp_get(sparx5_port, ifr);
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}
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}
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return phy_mii_ioctl(dev->phydev, ifr, cmd);
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}
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static const struct net_device_ops sparx5_port_netdev_ops = {
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.ndo_open = sparx5_port_open,
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.ndo_stop = sparx5_port_stop,
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.ndo_start_xmit = sparx5_port_xmit_impl,
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.ndo_set_rx_mode = sparx5_set_rx_mode,
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.ndo_get_phys_port_name = sparx5_port_get_phys_port_name,
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.ndo_set_mac_address = sparx5_set_mac_address,
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.ndo_validate_addr = eth_validate_addr,
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.ndo_get_stats64 = sparx5_get_stats64,
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.ndo_get_port_parent_id = sparx5_get_port_parent_id,
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.ndo_eth_ioctl = sparx5_port_ioctl,
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.ndo_setup_tc = sparx5_port_setup_tc,
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};
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bool sparx5_netdevice_check(const struct net_device *dev)
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{
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return dev && (dev->netdev_ops == &sparx5_port_netdev_ops);
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}
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struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno)
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{
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struct sparx5_port *spx5_port;
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struct net_device *ndev;
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ndev = devm_alloc_etherdev_mqs(sparx5->dev, sizeof(struct sparx5_port),
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SPX5_PRIOS, 1);
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if (!ndev)
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return ERR_PTR(-ENOMEM);
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ndev->hw_features |= NETIF_F_HW_TC;
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ndev->features |= NETIF_F_HW_TC;
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SET_NETDEV_DEV(ndev, sparx5->dev);
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spx5_port = netdev_priv(ndev);
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spx5_port->ndev = ndev;
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spx5_port->sparx5 = sparx5;
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spx5_port->portno = portno;
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ndev->netdev_ops = &sparx5_port_netdev_ops;
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ndev->ethtool_ops = &sparx5_ethtool_ops;
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eth_hw_addr_gen(ndev, sparx5->base_mac, portno + 1);
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return ndev;
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}
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int sparx5_register_netdevs(struct sparx5 *sparx5)
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{
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int portno;
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int err;
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for (portno = 0; portno < SPX5_PORTS; portno++)
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if (sparx5->ports[portno]) {
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err = register_netdev(sparx5->ports[portno]->ndev);
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if (err) {
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dev_err(sparx5->dev,
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"port: %02u: netdev registration failed\n",
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portno);
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return err;
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}
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sparx5_port_inj_timer_setup(sparx5->ports[portno]);
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}
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return 0;
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}
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void sparx5_destroy_netdevs(struct sparx5 *sparx5)
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{
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struct sparx5_port *port;
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int portno;
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for (portno = 0; portno < SPX5_PORTS; portno++) {
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port = sparx5->ports[portno];
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if (port && port->phylink) {
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/* Disconnect the phy */
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rtnl_lock();
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sparx5_port_stop(port->ndev);
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phylink_disconnect_phy(port->phylink);
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rtnl_unlock();
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phylink_destroy(port->phylink);
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port->phylink = NULL;
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}
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}
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}
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void sparx5_unregister_netdevs(struct sparx5 *sparx5)
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{
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int portno;
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for (portno = 0; portno < SPX5_PORTS; portno++)
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if (sparx5->ports[portno])
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unregister_netdev(sparx5->ports[portno]->ndev);
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}
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