597 lines
15 KiB
C
597 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include "sparx5_main_regs.h"
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#include "sparx5_main.h"
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/* QSYS calendar information */
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#define SPX5_PORTS_PER_CALREG 10 /* Ports mapped in a calendar register */
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#define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */
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/* DSM calendar information */
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#define SPX5_DSM_CAL_LEN 64
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#define SPX5_DSM_CAL_EMPTY 0xFFFF
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#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13
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#define SPX5_DSM_CAL_TAXIS 8
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#define SPX5_DSM_CAL_BW_LOSS 553
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#define SPX5_TAXI_PORT_MAX 70
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#define SPEED_12500 12500
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/* Maps from taxis to port numbers */
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static u32 sparx5_taxi_ports[SPX5_DSM_CAL_TAXIS][SPX5_DSM_CAL_MAX_DEVS_PER_TAXI] = {
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{57, 12, 0, 1, 2, 16, 17, 18, 19, 20, 21, 22, 23},
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{58, 13, 3, 4, 5, 24, 25, 26, 27, 28, 29, 30, 31},
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{59, 14, 6, 7, 8, 32, 33, 34, 35, 36, 37, 38, 39},
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{60, 15, 9, 10, 11, 40, 41, 42, 43, 44, 45, 46, 47},
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{61, 48, 49, 50, 99, 99, 99, 99, 99, 99, 99, 99, 99},
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{62, 51, 52, 53, 99, 99, 99, 99, 99, 99, 99, 99, 99},
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{56, 63, 54, 55, 99, 99, 99, 99, 99, 99, 99, 99, 99},
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{64, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99},
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};
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struct sparx5_calendar_data {
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u32 schedule[SPX5_DSM_CAL_LEN];
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u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
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u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
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u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
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u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI];
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u32 new_slots[SPX5_DSM_CAL_LEN];
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u32 temp_sched[SPX5_DSM_CAL_LEN];
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u32 indices[SPX5_DSM_CAL_LEN];
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u32 short_list[SPX5_DSM_CAL_LEN];
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u32 long_list[SPX5_DSM_CAL_LEN];
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};
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static u32 sparx5_target_bandwidth(struct sparx5 *sparx5)
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{
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switch (sparx5->target_ct) {
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case SPX5_TARGET_CT_7546:
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case SPX5_TARGET_CT_7546TSN:
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return 65000;
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case SPX5_TARGET_CT_7549:
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case SPX5_TARGET_CT_7549TSN:
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return 91000;
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case SPX5_TARGET_CT_7552:
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case SPX5_TARGET_CT_7552TSN:
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return 129000;
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case SPX5_TARGET_CT_7556:
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case SPX5_TARGET_CT_7556TSN:
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return 161000;
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case SPX5_TARGET_CT_7558:
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case SPX5_TARGET_CT_7558TSN:
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return 201000;
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default:
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return 0;
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}
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}
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/* This is used in calendar configuration */
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enum sparx5_cal_bw {
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SPX5_CAL_SPEED_NONE = 0,
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SPX5_CAL_SPEED_1G = 1,
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SPX5_CAL_SPEED_2G5 = 2,
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SPX5_CAL_SPEED_5G = 3,
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SPX5_CAL_SPEED_10G = 4,
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SPX5_CAL_SPEED_25G = 5,
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SPX5_CAL_SPEED_0G5 = 6,
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SPX5_CAL_SPEED_12G5 = 7
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};
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static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock)
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{
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switch (cclock) {
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case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 250000 / 3 */
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case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 500000 / 3 */
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case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */
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default: return 0;
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}
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return 0;
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}
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static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed)
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{
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switch (speed) {
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case SPX5_CAL_SPEED_1G: return 1000;
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case SPX5_CAL_SPEED_2G5: return 2500;
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case SPX5_CAL_SPEED_5G: return 5000;
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case SPX5_CAL_SPEED_10G: return 10000;
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case SPX5_CAL_SPEED_25G: return 25000;
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case SPX5_CAL_SPEED_0G5: return 500;
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case SPX5_CAL_SPEED_12G5: return 12500;
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default: return 0;
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}
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}
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static u32 sparx5_bandwidth_to_calendar(u32 bw)
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{
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switch (bw) {
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case SPEED_10: return SPX5_CAL_SPEED_0G5;
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case SPEED_100: return SPX5_CAL_SPEED_0G5;
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case SPEED_1000: return SPX5_CAL_SPEED_1G;
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case SPEED_2500: return SPX5_CAL_SPEED_2G5;
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case SPEED_5000: return SPX5_CAL_SPEED_5G;
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case SPEED_10000: return SPX5_CAL_SPEED_10G;
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case SPEED_12500: return SPX5_CAL_SPEED_12G5;
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case SPEED_25000: return SPX5_CAL_SPEED_25G;
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case SPEED_UNKNOWN: return SPX5_CAL_SPEED_1G;
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default: return SPX5_CAL_SPEED_NONE;
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}
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}
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static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5,
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u32 portno)
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{
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struct sparx5_port *port;
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if (portno >= SPX5_PORTS) {
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/* Internal ports */
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if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) {
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/* Equals 1.25G */
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return SPX5_CAL_SPEED_2G5;
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} else if (portno == SPX5_PORT_VD0) {
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/* IPMC only idle BW */
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return SPX5_CAL_SPEED_NONE;
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} else if (portno == SPX5_PORT_VD1) {
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/* OAM only idle BW */
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return SPX5_CAL_SPEED_NONE;
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} else if (portno == SPX5_PORT_VD2) {
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/* IPinIP gets only idle BW */
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return SPX5_CAL_SPEED_NONE;
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}
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/* not in port map */
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return SPX5_CAL_SPEED_NONE;
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}
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/* Front ports - may be used */
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port = sparx5->ports[portno];
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if (!port)
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return SPX5_CAL_SPEED_NONE;
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return sparx5_bandwidth_to_calendar(port->conf.bandwidth);
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}
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/* Auto configure the QSYS calendar based on port configuration */
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int sparx5_config_auto_calendar(struct sparx5 *sparx5)
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{
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u32 cal[7], value, idx, portno;
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u32 max_core_bw;
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u32 total_bw = 0, used_port_bw = 0;
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int err = 0;
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enum sparx5_cal_bw spd;
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memset(cal, 0, sizeof(cal));
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max_core_bw = sparx5_clk_to_bandwidth(sparx5->coreclock);
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if (max_core_bw == 0) {
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dev_err(sparx5->dev, "Core clock not supported");
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return -EINVAL;
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}
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/* Setup the calendar with the bandwidth to each port */
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for (portno = 0; portno < SPX5_PORTS_ALL; portno++) {
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u64 reg, offset, this_bw;
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spd = sparx5_get_port_cal_speed(sparx5, portno);
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if (spd == SPX5_CAL_SPEED_NONE)
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continue;
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this_bw = sparx5_cal_speed_to_value(spd);
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if (portno < SPX5_PORTS)
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used_port_bw += this_bw;
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else
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/* Internal ports are granted half the value */
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this_bw = this_bw / 2;
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total_bw += this_bw;
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reg = portno;
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offset = do_div(reg, SPX5_PORTS_PER_CALREG);
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cal[reg] |= spd << (offset * SPX5_CALBITS_PER_PORT);
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}
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if (used_port_bw > sparx5_target_bandwidth(sparx5)) {
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dev_err(sparx5->dev,
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"Port BW %u above target BW %u\n",
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used_port_bw, sparx5_target_bandwidth(sparx5));
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return -EINVAL;
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}
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if (total_bw > max_core_bw) {
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dev_err(sparx5->dev,
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"Total BW %u above switch core BW %u\n",
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total_bw, max_core_bw);
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return -EINVAL;
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}
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/* Halt the calendar while changing it */
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spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),
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QSYS_CAL_CTRL_CAL_MODE,
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sparx5, QSYS_CAL_CTRL);
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/* Assign port bandwidth to auto calendar */
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for (idx = 0; idx < ARRAY_SIZE(cal); idx++)
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spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx));
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/* Increase grant rate of all ports to account for
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* core clock ppm deviations
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*/
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spx5_rmw(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(671), /* 672->671 */
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QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE,
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sparx5,
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QSYS_CAL_CTRL);
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/* Grant idle usage to VD 0-2 */
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for (idx = 2; idx < 5; idx++)
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spx5_wr(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(12),
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sparx5,
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HSCH_OUTB_SHARE_ENA(idx));
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/* Enable Auto mode */
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spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8),
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QSYS_CAL_CTRL_CAL_MODE,
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sparx5, QSYS_CAL_CTRL);
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/* Verify successful calendar config */
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value = spx5_rd(sparx5, QSYS_CAL_CTRL);
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if (QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(value)) {
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dev_err(sparx5->dev, "QSYS calendar error\n");
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err = -EINVAL;
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}
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return err;
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}
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static u32 sparx5_dsm_exb_gcd(u32 a, u32 b)
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{
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if (b == 0)
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return a;
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return sparx5_dsm_exb_gcd(b, a % b);
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}
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static u32 sparx5_dsm_cal_len(u32 *cal)
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{
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u32 idx = 0, len = 0;
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while (idx < SPX5_DSM_CAL_LEN) {
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if (cal[idx] != SPX5_DSM_CAL_EMPTY)
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len++;
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idx++;
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}
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return len;
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}
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static u32 sparx5_dsm_cp_cal(u32 *sched)
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{
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u32 idx = 0, tmp;
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while (idx < SPX5_DSM_CAL_LEN) {
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if (sched[idx] != SPX5_DSM_CAL_EMPTY) {
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tmp = sched[idx];
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sched[idx] = SPX5_DSM_CAL_EMPTY;
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return tmp;
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}
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idx++;
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}
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return SPX5_DSM_CAL_EMPTY;
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}
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static int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
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struct sparx5_calendar_data *data)
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{
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bool slow_mode;
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u32 gcd, idx, sum, min, factor;
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u32 num_of_slots, slot_spd, empty_slots;
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u32 taxi_bw, clk_period_ps;
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clk_period_ps = sparx5_clk_period(sparx5->coreclock);
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taxi_bw = 128 * 1000000 / clk_period_ps;
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slow_mode = !!(clk_period_ps > 2000);
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memcpy(data->taxi_ports, &sparx5_taxi_ports[taxi],
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sizeof(data->taxi_ports));
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for (idx = 0; idx < SPX5_DSM_CAL_LEN; idx++) {
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data->new_slots[idx] = SPX5_DSM_CAL_EMPTY;
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data->schedule[idx] = SPX5_DSM_CAL_EMPTY;
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data->temp_sched[idx] = SPX5_DSM_CAL_EMPTY;
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}
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/* Default empty calendar */
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data->schedule[0] = SPX5_DSM_CAL_MAX_DEVS_PER_TAXI;
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/* Map ports to taxi positions */
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for (idx = 0; idx < SPX5_DSM_CAL_MAX_DEVS_PER_TAXI; idx++) {
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u32 portno = data->taxi_ports[idx];
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if (portno < SPX5_TAXI_PORT_MAX) {
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data->taxi_speeds[idx] = sparx5_cal_speed_to_value
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(sparx5_get_port_cal_speed(sparx5, portno));
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} else {
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data->taxi_speeds[idx] = 0;
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}
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}
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sum = 0;
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min = 25000;
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for (idx = 0; idx < ARRAY_SIZE(data->taxi_speeds); idx++) {
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u32 jdx;
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sum += data->taxi_speeds[idx];
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if (data->taxi_speeds[idx] && data->taxi_speeds[idx] < min)
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min = data->taxi_speeds[idx];
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gcd = min;
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for (jdx = 0; jdx < ARRAY_SIZE(data->taxi_speeds); jdx++)
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gcd = sparx5_dsm_exb_gcd(gcd, data->taxi_speeds[jdx]);
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}
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if (sum == 0) /* Empty calendar */
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return 0;
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/* Make room for overhead traffic */
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factor = 100 * 100 * 1000 / (100 * 100 - SPX5_DSM_CAL_BW_LOSS);
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if (sum * factor > (taxi_bw * 1000)) {
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dev_err(sparx5->dev,
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"Taxi %u, Requested BW %u above available BW %u\n",
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taxi, sum, taxi_bw);
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return -EINVAL;
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}
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for (idx = 0; idx < 4; idx++) {
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u32 raw_spd;
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if (idx == 0)
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raw_spd = gcd / 5;
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else if (idx == 1)
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raw_spd = gcd / 2;
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else if (idx == 2)
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raw_spd = gcd;
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else
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raw_spd = min;
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slot_spd = raw_spd * factor / 1000;
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num_of_slots = taxi_bw / slot_spd;
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if (num_of_slots <= 64)
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break;
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}
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num_of_slots = num_of_slots > 64 ? 64 : num_of_slots;
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slot_spd = taxi_bw / num_of_slots;
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sum = 0;
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for (idx = 0; idx < ARRAY_SIZE(data->taxi_speeds); idx++) {
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u32 spd = data->taxi_speeds[idx];
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u32 adjusted_speed = data->taxi_speeds[idx] * factor / 1000;
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if (adjusted_speed > 0) {
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data->avg_dist[idx] = (128 * 1000000 * 10) /
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(adjusted_speed * clk_period_ps);
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} else {
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data->avg_dist[idx] = -1;
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}
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data->dev_slots[idx] = ((spd * factor / slot_spd) + 999) / 1000;
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if (spd != 25000 && (spd != 10000 || !slow_mode)) {
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if (num_of_slots < (5 * data->dev_slots[idx])) {
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dev_err(sparx5->dev,
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"Taxi %u, speed %u, Low slot sep.\n",
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taxi, spd);
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return -EINVAL;
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}
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}
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sum += data->dev_slots[idx];
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if (sum > num_of_slots) {
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dev_err(sparx5->dev,
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"Taxi %u with overhead factor %u\n",
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taxi, factor);
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return -EINVAL;
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}
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}
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empty_slots = num_of_slots - sum;
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for (idx = 0; idx < empty_slots; idx++)
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data->schedule[idx] = SPX5_DSM_CAL_MAX_DEVS_PER_TAXI;
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for (idx = 1; idx < num_of_slots; idx++) {
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u32 indices_len = 0;
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u32 slot, jdx, kdx, ts;
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s32 cnt;
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u32 num_of_old_slots, num_of_new_slots, tgt_score;
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for (slot = 0; slot < ARRAY_SIZE(data->dev_slots); slot++) {
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if (data->dev_slots[slot] == idx) {
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data->indices[indices_len] = slot;
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indices_len++;
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}
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}
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if (indices_len == 0)
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continue;
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kdx = 0;
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for (slot = 0; slot < idx; slot++) {
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for (jdx = 0; jdx < indices_len; jdx++, kdx++)
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data->new_slots[kdx] = data->indices[jdx];
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}
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for (slot = 0; slot < SPX5_DSM_CAL_LEN; slot++) {
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if (data->schedule[slot] == SPX5_DSM_CAL_EMPTY)
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break;
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}
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num_of_old_slots = slot;
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num_of_new_slots = kdx;
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cnt = 0;
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ts = 0;
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if (num_of_new_slots > num_of_old_slots) {
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memcpy(data->short_list, data->schedule,
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sizeof(data->short_list));
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memcpy(data->long_list, data->new_slots,
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sizeof(data->long_list));
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tgt_score = 100000 * num_of_old_slots /
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num_of_new_slots;
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} else {
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memcpy(data->short_list, data->new_slots,
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sizeof(data->short_list));
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memcpy(data->long_list, data->schedule,
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sizeof(data->long_list));
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tgt_score = 100000 * num_of_new_slots /
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num_of_old_slots;
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}
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while (sparx5_dsm_cal_len(data->short_list) > 0 ||
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sparx5_dsm_cal_len(data->long_list) > 0) {
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u32 act = 0;
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if (sparx5_dsm_cal_len(data->short_list) > 0) {
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data->temp_sched[ts] =
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sparx5_dsm_cp_cal(data->short_list);
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ts++;
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cnt += 100000;
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act = 1;
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}
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while (sparx5_dsm_cal_len(data->long_list) > 0 &&
|
|
cnt > 0) {
|
|
data->temp_sched[ts] =
|
|
sparx5_dsm_cp_cal(data->long_list);
|
|
ts++;
|
|
cnt -= tgt_score;
|
|
act = 1;
|
|
}
|
|
if (act == 0) {
|
|
dev_err(sparx5->dev,
|
|
"Error in DSM calendar calculation\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
for (slot = 0; slot < SPX5_DSM_CAL_LEN; slot++) {
|
|
if (data->temp_sched[slot] == SPX5_DSM_CAL_EMPTY)
|
|
break;
|
|
}
|
|
for (slot = 0; slot < SPX5_DSM_CAL_LEN; slot++) {
|
|
data->schedule[slot] = data->temp_sched[slot];
|
|
data->temp_sched[slot] = SPX5_DSM_CAL_EMPTY;
|
|
data->new_slots[slot] = SPX5_DSM_CAL_EMPTY;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int sparx5_dsm_calendar_check(struct sparx5 *sparx5,
|
|
struct sparx5_calendar_data *data)
|
|
{
|
|
u32 num_of_slots, idx, port;
|
|
int cnt, max_dist;
|
|
u32 slot_indices[SPX5_DSM_CAL_LEN], distances[SPX5_DSM_CAL_LEN];
|
|
u32 cal_length = sparx5_dsm_cal_len(data->schedule);
|
|
|
|
for (port = 0; port < SPX5_DSM_CAL_MAX_DEVS_PER_TAXI; port++) {
|
|
num_of_slots = 0;
|
|
max_dist = data->avg_dist[port];
|
|
for (idx = 0; idx < SPX5_DSM_CAL_LEN; idx++) {
|
|
slot_indices[idx] = SPX5_DSM_CAL_EMPTY;
|
|
distances[idx] = SPX5_DSM_CAL_EMPTY;
|
|
}
|
|
|
|
for (idx = 0; idx < cal_length; idx++) {
|
|
if (data->schedule[idx] == port) {
|
|
slot_indices[num_of_slots] = idx;
|
|
num_of_slots++;
|
|
}
|
|
}
|
|
|
|
slot_indices[num_of_slots] = slot_indices[0] + cal_length;
|
|
|
|
for (idx = 0; idx < num_of_slots; idx++) {
|
|
distances[idx] = (slot_indices[idx + 1] -
|
|
slot_indices[idx]) * 10;
|
|
}
|
|
|
|
for (idx = 0; idx < num_of_slots; idx++) {
|
|
u32 jdx, kdx;
|
|
|
|
cnt = distances[idx] - max_dist;
|
|
if (cnt < 0)
|
|
cnt = -cnt;
|
|
kdx = 0;
|
|
for (jdx = (idx + 1) % num_of_slots;
|
|
jdx != idx;
|
|
jdx = (jdx + 1) % num_of_slots, kdx++) {
|
|
cnt = cnt + distances[jdx] - max_dist;
|
|
if (cnt < 0)
|
|
cnt = -cnt;
|
|
if (cnt > max_dist)
|
|
goto check_err;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
check_err:
|
|
dev_err(sparx5->dev,
|
|
"Port %u: distance %u above limit %d\n",
|
|
port, cnt, max_dist);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi,
|
|
struct sparx5_calendar_data *data)
|
|
{
|
|
u32 idx;
|
|
u32 cal_len = sparx5_dsm_cal_len(data->schedule), len;
|
|
|
|
spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1),
|
|
sparx5,
|
|
DSM_TAXI_CAL_CFG(taxi));
|
|
for (idx = 0; idx < cal_len; idx++) {
|
|
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx),
|
|
DSM_TAXI_CAL_CFG_CAL_IDX,
|
|
sparx5,
|
|
DSM_TAXI_CAL_CFG(taxi));
|
|
spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(data->schedule[idx]),
|
|
DSM_TAXI_CAL_CFG_CAL_PGM_VAL,
|
|
sparx5,
|
|
DSM_TAXI_CAL_CFG(taxi));
|
|
}
|
|
spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0),
|
|
sparx5,
|
|
DSM_TAXI_CAL_CFG(taxi));
|
|
len = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(spx5_rd(sparx5,
|
|
DSM_TAXI_CAL_CFG(taxi)));
|
|
if (len != cal_len - 1)
|
|
goto update_err;
|
|
return 0;
|
|
update_err:
|
|
dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Configure the DSM calendar based on port configuration */
|
|
int sparx5_config_dsm_calendar(struct sparx5 *sparx5)
|
|
{
|
|
int taxi;
|
|
struct sparx5_calendar_data *data;
|
|
int err = 0;
|
|
|
|
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
for (taxi = 0; taxi < SPX5_DSM_CAL_TAXIS; ++taxi) {
|
|
err = sparx5_dsm_calendar_calc(sparx5, taxi, data);
|
|
if (err) {
|
|
dev_err(sparx5->dev, "DSM calendar calculation failed\n");
|
|
goto cal_out;
|
|
}
|
|
err = sparx5_dsm_calendar_check(sparx5, data);
|
|
if (err) {
|
|
dev_err(sparx5->dev, "DSM calendar check failed\n");
|
|
goto cal_out;
|
|
}
|
|
err = sparx5_dsm_calendar_update(sparx5, taxi, data);
|
|
if (err) {
|
|
dev_err(sparx5->dev, "DSM calendar update failed\n");
|
|
goto cal_out;
|
|
}
|
|
}
|
|
cal_out:
|
|
kfree(data);
|
|
return err;
|
|
}
|