276 lines
9.5 KiB
C
276 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_MMU_8XX_H_
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#define _ASM_POWERPC_MMU_8XX_H_
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/*
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* PPC8xx support
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*/
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/* Control/status registers for the MPC8xx.
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* A write operation to these registers causes serialized access.
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* During software tablewalk, the registers used perform mask/shift-add
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* operations when written/read. A TLB entry is created when the Mx_RPN
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* is written, and the contents of several registers are used to
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* create the entry.
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*/
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#define SPRN_MI_CTR 784 /* Instruction TLB control register */
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#define MI_GPM 0x80000000 /* Set domain manager mode */
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#define MI_PPM 0x40000000 /* Set subpage protection */
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#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
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#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
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#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
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#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
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/* These are the Ks and Kp from the PowerPC books. For proper operation,
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* Ks = 0, Kp = 1.
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*/
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#define SPRN_MI_AP 786
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#define MI_Ks 0x80000000 /* Should not be set */
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#define MI_Kp 0x40000000 /* Should always be set */
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/*
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* All pages' PP data bits are set to either 001 or 011 by copying _PAGE_EXEC
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* into bit 21 in the ITLBmiss handler (bit 21 is the middle bit), which means
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* respectively NA for All or X for Supervisor and no access for User.
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* Then we use the APG to say whether accesses are according to Page rules or
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* "all Supervisor" rules (Access to all)
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* _PAGE_ACCESSED is also managed via APG. When _PAGE_ACCESSED is not set, say
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* "all User" rules, that will lead to NA for all.
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* Therefore, we define 4 APG groups. lsb is _PAGE_ACCESSED
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* 0 => Kernel => 11 (all accesses performed according as user iaw page definition)
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* 1 => Kernel+Accessed => 01 (all accesses performed according to page definition)
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* 2 => User => 11 (all accesses performed according as user iaw page definition)
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* 3 => User+Accessed => 10 (all accesses performed according to swaped page definition) for KUEP
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* 4-15 => Not Used
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*/
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#define MI_APG_INIT 0xde000000
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/* The effective page number register. When read, contains the information
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* about the last instruction TLB miss. When MI_RPN is written, bits in
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* this register are used to create the TLB entry.
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*/
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#define SPRN_MI_EPN 787
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#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
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#define MI_EVALID 0x00000200 /* Entry is valid */
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#define MI_ASIDMASK 0x0000000f /* ASID match value */
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/* Reset value is undefined */
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/* A "level 1" or "segment" or whatever you want to call it register.
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* For the instruction TLB, it contains bits that get loaded into the
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* TLB entry when the MI_RPN is written.
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*/
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#define SPRN_MI_TWC 789
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#define MI_APG 0x000001e0 /* Access protection group (0) */
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#define MI_GUARDED 0x00000010 /* Guarded storage */
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#define MI_PSMASK 0x0000000c /* Mask of page size bits */
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#define MI_PS8MEG 0x0000000c /* 8M page size */
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#define MI_PS512K 0x00000004 /* 512K page size */
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#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
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#define MI_SVALID 0x00000001 /* Segment entry is valid */
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/* Reset value is undefined */
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/* Real page number. Defined by the pte. Writing this register
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* causes a TLB entry to be created for the instruction TLB, using
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* additional information from the MI_EPN, and MI_TWC registers.
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*/
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#define SPRN_MI_RPN 790
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#define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
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/* Define an RPN value for mapping kernel memory to large virtual
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* pages for boot initialization. This has real page number of 0,
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* large page size, shared page, cache enabled, and valid.
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* Also mark all subpages valid and write access.
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*/
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#define MI_BOOTINIT 0x000001fd
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#define SPRN_MD_CTR 792 /* Data TLB control register */
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#define MD_GPM 0x80000000 /* Set domain manager mode */
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#define MD_PPM 0x40000000 /* Set subpage protection */
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#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
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#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
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#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
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#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
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#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
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#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
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#define SPRN_M_CASID 793 /* Address space ID (context) to match */
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#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
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/* These are the Ks and Kp from the PowerPC books. For proper operation,
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* Ks = 0, Kp = 1.
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*/
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#define SPRN_MD_AP 794
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#define MD_Ks 0x80000000 /* Should not be set */
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#define MD_Kp 0x40000000 /* Should always be set */
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/* See explanation above at the definition of MI_APG_INIT */
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#define MD_APG_INIT 0xdc000000
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#define MD_APG_KUAP 0xde000000
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/* The effective page number register. When read, contains the information
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* about the last instruction TLB miss. When MD_RPN is written, bits in
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* this register are used to create the TLB entry.
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*/
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#define SPRN_MD_EPN 795
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#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
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#define MD_EVALID 0x00000200 /* Entry is valid */
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#define MD_ASIDMASK 0x0000000f /* ASID match value */
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/* Reset value is undefined */
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/* The pointer to the base address of the first level page table.
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* During a software tablewalk, reading this register provides the address
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* of the entry associated with MD_EPN.
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*/
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#define SPRN_M_TWB 796
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#define M_L1TB 0xfffff000 /* Level 1 table base address */
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#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
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/* Reset value is undefined */
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/* A "level 1" or "segment" or whatever you want to call it register.
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* For the data TLB, it contains bits that get loaded into the TLB entry
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* when the MD_RPN is written. It is also provides the hardware assist
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* for finding the PTE address during software tablewalk.
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*/
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#define SPRN_MD_TWC 797
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#define MD_L2TB 0xfffff000 /* Level 2 table base address */
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#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
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#define MD_APG 0x000001e0 /* Access protection group (0) */
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#define MD_GUARDED 0x00000010 /* Guarded storage */
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#define MD_PSMASK 0x0000000c /* Mask of page size bits */
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#define MD_PS8MEG 0x0000000c /* 8M page size */
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#define MD_PS512K 0x00000004 /* 512K page size */
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#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
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#define MD_WT 0x00000002 /* Use writethrough page attribute */
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#define MD_SVALID 0x00000001 /* Segment entry is valid */
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/* Reset value is undefined */
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/* Real page number. Defined by the pte. Writing this register
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* causes a TLB entry to be created for the data TLB, using
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* additional information from the MD_EPN, and MD_TWC registers.
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*/
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#define SPRN_MD_RPN 798
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#define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
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/* This is a temporary storage register that could be used to save
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* a processor working register during a tablewalk.
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*/
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#define SPRN_M_TW 799
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#if defined(CONFIG_PPC_4K_PAGES)
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#define mmu_virtual_psize MMU_PAGE_4K
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#elif defined(CONFIG_PPC_16K_PAGES)
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#define mmu_virtual_psize MMU_PAGE_16K
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#define PTE_FRAG_NR 4
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#define PTE_FRAG_SIZE_SHIFT 12
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#define PTE_FRAG_SIZE (1UL << 12)
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#else
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#error "Unsupported PAGE_SIZE"
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#endif
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#define mmu_linear_psize MMU_PAGE_8M
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#define MODULES_VADDR (PAGE_OFFSET - SZ_256M)
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#define MODULES_END PAGE_OFFSET
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#ifndef __ASSEMBLY__
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#include <linux/mmdebug.h>
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#include <linux/sizes.h>
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void mmu_pin_tlb(unsigned long top, bool readonly);
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typedef struct {
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unsigned int id;
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unsigned int active;
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void __user *vdso;
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void *pte_frag;
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} mm_context_t;
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#define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)
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#define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))
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/* Page size definitions, common between 32 and 64-bit
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* penc : is the pte encoding mask
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*
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*/
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struct mmu_psize_def {
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unsigned int shift; /* number of bits */
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unsigned int enc; /* PTE encoding */
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unsigned int ind; /* Corresponding indirect page size shift */
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unsigned int flags;
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#define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
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#define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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static inline int shift_to_mmu_psize(unsigned int shift)
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{
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int psize;
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for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
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if (mmu_psize_defs[psize].shift == shift)
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return psize;
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return -1;
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}
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static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
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{
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if (mmu_psize_defs[mmu_psize].shift)
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return mmu_psize_defs[mmu_psize].shift;
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BUG();
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}
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static inline bool arch_vmap_try_size(unsigned long addr, unsigned long end, u64 pfn,
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unsigned int max_page_shift, unsigned long size)
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{
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if (end - addr < size)
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return false;
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if ((1UL << max_page_shift) < size)
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return false;
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if (!IS_ALIGNED(addr, size))
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return false;
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if (!IS_ALIGNED(PFN_PHYS(pfn), size))
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return false;
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return true;
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}
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static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, unsigned long end,
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u64 pfn, unsigned int max_page_shift)
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{
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if (arch_vmap_try_size(addr, end, pfn, max_page_shift, SZ_512K))
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return SZ_512K;
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if (PAGE_SIZE == SZ_16K)
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return SZ_16K;
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if (arch_vmap_try_size(addr, end, pfn, max_page_shift, SZ_16K))
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return SZ_16K;
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return PAGE_SIZE;
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}
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#define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size
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static inline int arch_vmap_pte_supported_shift(unsigned long size)
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{
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if (size >= SZ_512K)
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return 19;
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else if (size >= SZ_16K)
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return 14;
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else
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return PAGE_SHIFT;
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}
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#define arch_vmap_pte_supported_shift arch_vmap_pte_supported_shift
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/* patch sites */
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extern s32 patch__itlbmiss_exit_1, patch__dtlbmiss_exit_1;
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extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf;
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_MMU_8XX_H_ */
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