296 lines
7.5 KiB
C
296 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
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#define _ASM_POWERPC_BOOK3S_64_MMU_H_
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#include <asm/page.h>
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#ifndef __ASSEMBLY__
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def {
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unsigned int shift; /* number of bits */
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int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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unsigned long h_rpt_pgsize; /* H_RPT_INVALIDATE page size encoding */
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union {
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
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};
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};
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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#endif /* __ASSEMBLY__ */
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/* 64-bit classic hash table MMU */
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#include <asm/book3s/64/mmu-hash.h>
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#ifndef __ASSEMBLY__
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/*
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* ISA 3.0 partition and process table entry format
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*/
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struct prtb_entry {
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__be64 prtb0;
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__be64 prtb1;
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};
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extern struct prtb_entry *process_tb;
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struct patb_entry {
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__be64 patb0;
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__be64 patb1;
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};
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extern struct patb_entry *partition_tb;
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/* Bits in patb0 field */
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#define PATB_HR (1UL << 63)
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#define RPDB_MASK 0x0fffffffffffff00UL
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#define RPDB_SHIFT (1UL << 8)
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#define RTS1_SHIFT 61 /* top 2 bits of radix tree size */
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#define RTS1_MASK (3UL << RTS1_SHIFT)
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#define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */
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#define RTS2_MASK (7UL << RTS2_SHIFT)
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#define RPDS_MASK 0x1f /* root page dir. size field */
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/* Bits in patb1 field */
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#define PATB_GR (1UL << 63) /* guest uses radix; must match HR */
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#define PRTS_MASK 0x1f /* process table size field */
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#define PRTB_MASK 0x0ffffffffffff000UL
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/* Number of supported LPID bits */
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extern unsigned int mmu_lpid_bits;
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/* Number of supported PID bits */
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extern unsigned int mmu_pid_bits;
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/* Base PID to allocate from */
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extern unsigned int mmu_base_pid;
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/*
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* memory block size used with radix translation.
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*/
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extern unsigned long __ro_after_init radix_mem_block_size;
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#define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
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#define PRTB_ENTRIES (1ul << mmu_pid_bits)
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#define PATB_SIZE_SHIFT (mmu_lpid_bits + 4)
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#define PATB_ENTRIES (1ul << mmu_lpid_bits)
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typedef unsigned long mm_context_id_t;
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struct spinlock;
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/* Maximum possible number of NPUs in a system. */
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#define NV_MAX_NPUS 8
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typedef struct {
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union {
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/*
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* We use id as the PIDR content for radix. On hash we can use
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* more than one id. The extended ids are used when we start
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* having address above 512TB. We allocate one extended id
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* for each 512TB. The new id is then used with the 49 bit
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* EA to build a new VA. We always use ESID_BITS_1T_MASK bits
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* from EA and new context ids to build the new VAs.
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*/
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mm_context_id_t id;
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#ifdef CONFIG_PPC_64S_HASH_MMU
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mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
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#endif
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};
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/* Number of bits in the mm_cpumask */
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atomic_t active_cpus;
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/* Number of users of the external (Nest) MMU */
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atomic_t copros;
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/* Number of user space windows opened in process mm_context */
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atomic_t vas_windows;
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#ifdef CONFIG_PPC_64S_HASH_MMU
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struct hash_mm_context *hash_context;
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#endif
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void __user *vdso;
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/*
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* pagetable fragment support
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*/
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void *pte_frag;
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void *pmd_frag;
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#ifdef CONFIG_SPAPR_TCE_IOMMU
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struct list_head iommu_group_mem_list;
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#endif
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#ifdef CONFIG_PPC_MEM_KEYS
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/*
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* Each bit represents one protection key.
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* bit set -> key allocated
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* bit unset -> key available for allocation
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*/
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u32 pkey_allocation_map;
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s16 execute_only_pkey; /* key holding execute-only protection */
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#endif
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} mm_context_t;
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#ifdef CONFIG_PPC_64S_HASH_MMU
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static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
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{
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return ctx->hash_context->user_psize;
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}
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static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
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{
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ctx->hash_context->user_psize = user_psize;
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}
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static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
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{
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return ctx->hash_context->low_slices_psize;
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}
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static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
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{
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return ctx->hash_context->high_slices_psize;
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}
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static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
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{
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return ctx->hash_context->slb_addr_limit;
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}
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static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)
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{
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ctx->hash_context->slb_addr_limit = limit;
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}
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static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
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{
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#ifdef CONFIG_PPC_64K_PAGES
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if (psize == MMU_PAGE_64K)
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return &ctx->hash_context->mask_64k;
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#endif
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#ifdef CONFIG_HUGETLB_PAGE
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if (psize == MMU_PAGE_16M)
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return &ctx->hash_context->mask_16m;
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if (psize == MMU_PAGE_16G)
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return &ctx->hash_context->mask_16g;
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#endif
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BUG_ON(psize != MMU_PAGE_4K);
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return &ctx->hash_context->mask_4k;
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}
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#ifdef CONFIG_PPC_SUBPAGE_PROT
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static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx)
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{
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return ctx->hash_context->spt;
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}
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#endif
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/*
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* The current system page and segment sizes
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*/
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_io_psize;
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#else /* CONFIG_PPC_64S_HASH_MMU */
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#ifdef CONFIG_PPC_64K_PAGES
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#define mmu_virtual_psize MMU_PAGE_64K
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#else
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#define mmu_virtual_psize MMU_PAGE_4K
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#endif
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#endif
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extern int mmu_linear_psize;
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extern int mmu_vmemmap_psize;
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/* MMU initialization */
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void mmu_early_init_devtree(void);
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void hash__early_init_devtree(void);
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void radix__early_init_devtree(void);
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#ifdef CONFIG_PPC_PKEY
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void pkey_early_init_devtree(void);
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#else
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static inline void pkey_early_init_devtree(void) {}
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#endif
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extern void hash__early_init_mmu(void);
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extern void radix__early_init_mmu(void);
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static inline void __init early_init_mmu(void)
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{
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if (radix_enabled())
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return radix__early_init_mmu();
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return hash__early_init_mmu();
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}
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extern void hash__early_init_mmu_secondary(void);
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extern void radix__early_init_mmu_secondary(void);
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static inline void early_init_mmu_secondary(void)
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{
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if (radix_enabled())
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return radix__early_init_mmu_secondary();
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return hash__early_init_mmu_secondary();
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}
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extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size);
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static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/*
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* Hash has more strict restrictions. At this point we don't
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* know which translations we will pick. Hence go with hash
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* restrictions.
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*/
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if (!early_radix_enabled())
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hash__setup_initial_memory_limit(first_memblock_base,
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first_memblock_size);
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}
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#ifdef CONFIG_PPC_PSERIES
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void __init radix_init_pseries(void);
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#else
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static inline void radix_init_pseries(void) { }
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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#define arch_clear_mm_cpumask_cpu(cpu, mm) \
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do { \
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if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { \
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atomic_dec(&(mm)->context.active_cpus); \
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cpumask_clear_cpu(cpu, mm_cpumask(mm)); \
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} \
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} while (0)
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void cleanup_cpu_mmu_context(void);
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#endif
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#ifdef CONFIG_PPC_64S_HASH_MMU
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static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
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{
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int index = ea >> MAX_EA_BITS_PER_CONTEXT;
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if (likely(index < ARRAY_SIZE(ctx->extended_id)))
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return ctx->extended_id[index];
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/* should never happen */
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WARN_ON(1);
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return 0;
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}
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static inline unsigned long get_user_vsid(mm_context_t *ctx,
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unsigned long ea, int ssize)
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{
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unsigned long context = get_user_context(ctx, ea);
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return get_vsid(context, ea, ssize);
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
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