621 lines
19 KiB
C
621 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H
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#define _ASM_POWERPC_BOOK3S_32_PGTABLE_H
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#include <asm-generic/pgtable-nopmd.h>
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/*
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* The "classic" 32-bit implementation of the PowerPC MMU uses a hash
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* table containing PTEs, together with a set of 16 segment registers,
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* to define the virtual to physical address mapping.
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*
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* We use the hash table as an extended TLB, i.e. a cache of currently
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* active mappings. We maintain a two-level page table tree, much
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* like that used by the i386, for the sake of the Linux memory
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* management code. Low-level assembler code in hash_low_32.S
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* (procedure hash_page) is responsible for extracting ptes from the
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* tree and putting them into the hash table when necessary, and
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* updating the accessed and modified bits in the page table tree.
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*/
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#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
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#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
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#define _PAGE_USER 0x004 /* usermode access allowed */
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#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
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#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x080 /* C: page changed */
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#define _PAGE_ACCESSED 0x100 /* R: page referenced */
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#define _PAGE_EXEC 0x200 /* software: exec allowed */
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#define _PAGE_RW 0x400 /* software: user write access allowed */
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#define _PAGE_SPECIAL 0x800 /* software: Special page */
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#ifdef CONFIG_PTE_64BIT
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/* We never clear the high word of the pte */
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#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
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#else
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#define _PTE_NONE_MASK _PAGE_HASHPTE
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#endif
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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/* And here we include common definitions */
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#define _PAGE_KERNEL_RO 0
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#define _PAGE_KERNEL_ROX (_PAGE_EXEC)
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW)
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
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#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
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#ifndef __ASSEMBLY__
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static inline bool pte_user(pte_t pte)
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{
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return pte_val(pte) & _PAGE_USER;
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}
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#endif /* __ASSEMBLY__ */
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/*
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* Location of the PFN in the PTE. Most 32-bit platforms use the same
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* as _PAGE_SHIFT here (ie, naturally aligned).
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* Platform who don't just pre-define the value so we don't override it here.
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*/
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#define PTE_RPN_SHIFT (PAGE_SHIFT)
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/*
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* The mask covered by the RPN must be a ULL on 32-bit platforms with
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* 64-bit PTEs.
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*/
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#ifdef CONFIG_PTE_64BIT
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#define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1))
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#define MAX_POSSIBLE_PHYSMEM_BITS 36
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#else
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#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
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#define MAX_POSSIBLE_PHYSMEM_BITS 32
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#endif
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/*
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* _PAGE_CHG_MASK masks of bits that are to be preserved across
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* pgprot changes.
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*/
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#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HASHPTE | _PAGE_DIRTY | \
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_PAGE_ACCESSED | _PAGE_SPECIAL)
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/*
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* We define 2 sets of base prot bits, one for basic pages (ie,
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* cacheable kernel and user pages) and one for non cacheable
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* pages. We always set _PAGE_COHERENT when SMP is enabled or
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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/*
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* Permission masks used to generate the __P and __S table.
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*
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* Note:__pgprot is defined in arch/powerpc/include/asm/page.h
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*
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* Write permissions imply read permissions for now.
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*/
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#define PAGE_NONE __pgprot(_PAGE_BASE)
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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/* Permission masks used for kernel mappings */
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#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
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#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE)
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#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE | _PAGE_GUARDED)
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#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
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#define PTE_INDEX_SIZE PTE_SHIFT
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#define PMD_INDEX_SIZE 0
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#define PUD_INDEX_SIZE 0
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#define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
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#define PMD_CACHE_INDEX PMD_INDEX_SIZE
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#define PUD_CACHE_INDEX PUD_INDEX_SIZE
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE 0
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#define PUD_TABLE_SIZE 0
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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/* Bits to mask out from a PMD to get to the PTE page */
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#define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1)
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/*
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* The normal case is that PTEs are 32-bits and we have a 1-page
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* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
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*
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* For any >32-bit physical address platform, we can use the following
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* two level page table layout where the pgdir is 8KB and the MS 13 bits
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* are an index to the second level table. The combined pgdir/pmd first
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* level has 2048 entries and the second level has 512 64-bit PTE entries.
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* -Matt
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*/
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/* PGDIR_SHIFT determines what a top-level page table entry can map */
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#define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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#ifndef __ASSEMBLY__
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int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot);
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void unmap_kernel_page(unsigned long va);
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#endif /* !__ASSEMBLY__ */
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/*
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* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
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* value (for now) on others, from where we can start layout kernel
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* virtual space that goes below PKMAP and FIXMAP
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*/
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#include <asm/fixmap.h>
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/*
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* ioremap_bot starts at that address. Early ioremaps move down from there,
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* until mem_init() at which point this becomes the top of the vmalloc
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* and ioremap space
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*/
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#ifdef CONFIG_HIGHMEM
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#define IOREMAP_TOP PKMAP_BASE
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#else
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#define IOREMAP_TOP FIXADDR_START
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#endif
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/* PPC32 shares vmalloc area with ioremap */
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#define IOREMAP_START VMALLOC_START
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#define IOREMAP_END VMALLOC_END
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/*
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* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 16MB value just means that there will be a 64MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*
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* We no longer map larger than phys RAM with the BATs so we don't have
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* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
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* about clashes between our early calls to ioremap() that start growing down
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* from ioremap_base being run into the VM area allocations (growing upwards
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* from VMALLOC_START). For this reason we have ioremap_bot to check when
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* we actually run into our mappings setup in the early boot with the VM
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* system. This really does become a problem for machines with good amounts
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* of RAM. -- Cort
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*/
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#define VMALLOC_OFFSET (0x1000000) /* 16M */
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#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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#ifdef CONFIG_KASAN_VMALLOC
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#define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
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#else
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#define VMALLOC_END ioremap_bot
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#endif
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#define MODULES_END ALIGN_DOWN(PAGE_OFFSET, SZ_256M)
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#define MODULES_VADDR (MODULES_END - SZ_256M)
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/threads.h>
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/* Bits to mask out from a PGD to get to the PUD page */
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#define PGD_MASKED_BITS 0
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
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(unsigned long long)pte_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* Bits in a linux-style PTE. These match the bits in the
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* (hardware-defined) PowerPC PTE as closely as possible.
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*/
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#define pte_clear(mm, addr, ptep) \
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do { pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0); } while (0)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
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#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
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static inline void pmd_clear(pmd_t *pmdp)
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{
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*pmdp = __pmd(0);
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}
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/*
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* When flushing the tlb entry for a page, we also need to flush the hash
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* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
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*/
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extern int flush_hash_pages(unsigned context, unsigned long va,
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unsigned long pmdval, int count);
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/* Add an HPTE to the hash table */
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extern void add_hash_page(unsigned context, unsigned long va,
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unsigned long pmdval);
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/* Flush an entry from the TLB/hash table */
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static inline void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, unsigned long addr)
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{
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
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unsigned long ptephys = __pa(ptep) & PAGE_MASK;
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flush_hash_pages(mm->context.id, addr, ptephys, 1);
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}
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}
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/*
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* PTE updates. This function is called whenever an existing
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* valid PTE is updated. This does -not- include set_pte_at()
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* which nowadays only sets a new PTE.
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*
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* Depending on the type of MMU, we may need to use atomic updates
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* and the PTE may be either 32 or 64 bit wide. In the later case,
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* when using atomic updates, only the low part of the PTE is
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* accessed atomically.
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*/
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static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
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unsigned long clr, unsigned long set, int huge)
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{
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pte_basic_t old;
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
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unsigned long tmp;
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asm volatile(
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#ifndef CONFIG_PTE_64BIT
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"1: lwarx %0, 0, %3\n"
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" andc %1, %0, %4\n"
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#else
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"1: lwarx %L0, 0, %3\n"
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" lwz %0, -4(%3)\n"
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" andc %1, %L0, %4\n"
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#endif
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" or %1, %1, %5\n"
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" stwcx. %1, 0, %3\n"
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" bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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#ifndef CONFIG_PTE_64BIT
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: "r" (p),
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#else
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: "b" ((unsigned long)(p) + 4),
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#endif
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"r" (clr), "r" (set), "m" (*p)
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: "cc" );
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} else {
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old = pte_val(*p);
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*p = __pte((old & ~(pte_basic_t)clr) | set);
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}
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return old;
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}
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/*
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* 2.6 calls this without flushing the TLB entry; this is wrong
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* for our hash-based implementation, we fix that up here.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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unsigned long old;
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old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
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if (old & _PAGE_HASHPTE)
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flush_hash_entry(mm, ptep, addr);
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return (old & _PAGE_ACCESSED) != 0;
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}
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#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
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__ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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return __pte(pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0));
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}
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
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}
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static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
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pte_t *ptep, pte_t entry,
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unsigned long address,
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int psize)
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{
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unsigned long set = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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pte_update(vma->vm_mm, address, ptep, 0, set, 0);
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flush_tlb_page(vma, address);
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}
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#define __HAVE_ARCH_PTE_SAME
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#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
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#define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT)
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#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
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/*
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* Encode and decode a swap entry.
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* Note that the bits we use in a PTE for representing a swap entry
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* must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
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* -- paulus
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*/
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#define __swp_type(entry) ((entry).val & 0x1f)
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#define __swp_offset(entry) ((entry).val >> 5)
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#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
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/* Generic accessors to PTE bits */
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static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
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static inline int pte_read(pte_t pte) { return 1; }
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static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
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static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
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static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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static inline bool pte_hw_valid(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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static inline bool pte_hashpte(pte_t pte)
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{
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return !!(pte_val(pte) & _PAGE_HASHPTE);
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}
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static inline bool pte_ci(pte_t pte)
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{
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return !!(pte_val(pte) & _PAGE_NO_CACHE);
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}
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/*
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* We only find page table entry in the last level
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* Hence no need for other accessors
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*/
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#define pte_access_permitted pte_access_permitted
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static inline bool pte_access_permitted(pte_t pte, bool write)
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{
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/*
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* A read-only access is controlled by _PAGE_USER bit.
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* We have _PAGE_READ set for WRITE and EXECUTE
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*/
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if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
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return false;
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if (write && !pte_write(pte))
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return false;
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return true;
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}
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
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{
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot));
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return pte_val(pte) >> PTE_RPN_SHIFT;
|
|
}
|
|
|
|
/* Generic modifiers for PTE bits */
|
|
static inline pte_t pte_wrprotect(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) & ~_PAGE_RW);
|
|
}
|
|
|
|
static inline pte_t pte_exprotect(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) & ~_PAGE_EXEC);
|
|
}
|
|
|
|
static inline pte_t pte_mkclean(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) & ~_PAGE_DIRTY);
|
|
}
|
|
|
|
static inline pte_t pte_mkold(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
|
|
}
|
|
|
|
static inline pte_t pte_mkexec(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) | _PAGE_EXEC);
|
|
}
|
|
|
|
static inline pte_t pte_mkpte(pte_t pte)
|
|
{
|
|
return pte;
|
|
}
|
|
|
|
static inline pte_t pte_mkwrite(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) | _PAGE_RW);
|
|
}
|
|
|
|
static inline pte_t pte_mkdirty(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) | _PAGE_DIRTY);
|
|
}
|
|
|
|
static inline pte_t pte_mkyoung(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) | _PAGE_ACCESSED);
|
|
}
|
|
|
|
static inline pte_t pte_mkspecial(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) | _PAGE_SPECIAL);
|
|
}
|
|
|
|
static inline pte_t pte_mkhuge(pte_t pte)
|
|
{
|
|
return pte;
|
|
}
|
|
|
|
static inline pte_t pte_mkprivileged(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) & ~_PAGE_USER);
|
|
}
|
|
|
|
static inline pte_t pte_mkuser(pte_t pte)
|
|
{
|
|
return __pte(pte_val(pte) | _PAGE_USER);
|
|
}
|
|
|
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
{
|
|
return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
|
|
}
|
|
|
|
|
|
|
|
/* This low level function performs the actual PTE insertion
|
|
* Setting the PTE depends on the MMU type and other factors. It's
|
|
* an horrible mess that I'm not going to try to clean up now but
|
|
* I'm keeping it in one place rather than spread around
|
|
*/
|
|
static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|
pte_t *ptep, pte_t pte, int percpu)
|
|
{
|
|
#if defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
|
|
/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
|
|
* helper pte_update() which does an atomic update. We need to do that
|
|
* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
|
|
* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
|
|
* the hash bits instead (ie, same as the non-SMP case)
|
|
*/
|
|
if (percpu)
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
else
|
|
pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, pte_val(pte), 0);
|
|
|
|
#elif defined(CONFIG_PTE_64BIT)
|
|
/* Second case is 32-bit with 64-bit PTE. In this case, we
|
|
* can just store as long as we do the two halves in the right order
|
|
* with a barrier in between. This is possible because we take care,
|
|
* in the hash code, to pre-invalidate if the PTE was already hashed,
|
|
* which synchronizes us with any concurrent invalidation.
|
|
* In the percpu case, we also fallback to the simple update preserving
|
|
* the hash bits
|
|
*/
|
|
if (percpu) {
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
return;
|
|
}
|
|
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
|
flush_hash_entry(mm, ptep, addr);
|
|
__asm__ __volatile__("\
|
|
stw%X0 %2,%0\n\
|
|
eieio\n\
|
|
stw%X1 %L2,%1"
|
|
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
|
: "r" (pte) : "memory");
|
|
|
|
#else
|
|
/* Third case is 32-bit hash table in UP mode, we need to preserve
|
|
* the _PAGE_HASHPTE bit since we may not have invalidated the previous
|
|
* translation in the hash yet (done in a subsequent flush_tlb_xxx())
|
|
* and see we need to keep track that this PTE needs invalidating
|
|
*/
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Macro to mark a page protection value as "uncacheable".
|
|
*/
|
|
|
|
#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
|
|
_PAGE_WRITETHRU)
|
|
|
|
#define pgprot_noncached pgprot_noncached
|
|
static inline pgprot_t pgprot_noncached(pgprot_t prot)
|
|
{
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED);
|
|
}
|
|
|
|
#define pgprot_noncached_wc pgprot_noncached_wc
|
|
static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
|
|
{
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
_PAGE_NO_CACHE);
|
|
}
|
|
|
|
#define pgprot_cached pgprot_cached
|
|
static inline pgprot_t pgprot_cached(pgprot_t prot)
|
|
{
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
_PAGE_COHERENT);
|
|
}
|
|
|
|
#define pgprot_cached_wthru pgprot_cached_wthru
|
|
static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
|
|
{
|
|
return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
|
|
_PAGE_COHERENT | _PAGE_WRITETHRU);
|
|
}
|
|
|
|
#define pgprot_cached_noncoherent pgprot_cached_noncoherent
|
|
static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
|
|
{
|
|
return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
|
|
}
|
|
|
|
#define pgprot_writecombine pgprot_writecombine
|
|
static inline pgprot_t pgprot_writecombine(pgprot_t prot)
|
|
{
|
|
return pgprot_noncached_wc(prot);
|
|
}
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */
|