745 lines
13 KiB
Plaintext
745 lines
13 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Draak board
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*
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* Copyright (C) 2016-2018 Renesas Electronics Corp.
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* Copyright (C) 2017 Glider bvba
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Renesas Draak board";
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compatible = "renesas,draak";
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aliases {
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serial0 = &scif2;
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ethernet0 = &avb;
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};
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audio_clkout: audio-clkout {
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/*
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* This is same as <&rcar_sound 0>
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* but needed to avoid cs2000/rcar_sound probe dead-lock
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*/
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 50000>;
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brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
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default-brightness-level = <10>;
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power-supply = <®_12p0v>;
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enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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stdout-path = "serial0:115200n8";
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};
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composite-in {
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compatible = "composite-video-connector";
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port {
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composite_con_in: endpoint {
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remote-endpoint = <&adv7180_in>;
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};
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};
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};
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hdmi-in {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&adv7612_in>;
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};
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};
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_out: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&keys_pins>;
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pinctrl-names = "default";
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key-1 {
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gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_1>;
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label = "SW56-1";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-2 {
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gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_2>;
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label = "SW56-2";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-3 {
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gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_3>;
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label = "SW56-3";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-4 {
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gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_4>;
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label = "SW56-4";
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wakeup-source;
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debounce-interval = <20>;
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};
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};
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lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <®_3p3v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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thc63lvd1024_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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port@2 {
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reg = <2>;
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thc63lvd1024_out: endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x18000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_12p0v: regulator-12p0v {
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compatible = "regulator-fixed";
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regulator-name = "D12.0V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sound_card: sound {
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compatible = "audio-graph-card";
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dais = <&rsnd_port0 /* ak4613 */
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/* HDMI is not yet supported */
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>;
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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x12_clk: x12 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <74250000>;
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};
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x19_clk: x19 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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};
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&audio_clk_b {
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/*
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* X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
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* and R-Car Sound uses AUDIO_CLKB.
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* Note is that schematic indicates VI4_FIELD conection only
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* not AUDIO_CLKB at SoC page.
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* And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
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* SW60 should be 1-2.
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*/
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clock-frequency = <22579200>;
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};
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&avb {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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status = "okay";
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio5>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
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/*
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* TX clock internal delay mode is required for reliable
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* 1Gbps communication using the KSZ9031RNX phy present on
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* the Draak board, however, TX clock internal delay mode
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* isn't supported on R-Car D3(e). Thus, limit speed to
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* 100Mbps for reliable communication.
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*/
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max-speed = <100>;
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};
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&can1 {
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pinctrl-0 = <&can1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&x12_clk>;
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clock-names = "du.0", "du.1", "dclkin.0";
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ports {
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port@0 {
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du_out_rgb: endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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&ehci0 {
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dr_mode = "host";
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <48000000>;
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};
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&hsusb {
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dr_mode = "host";
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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ak4613: codec@10 {
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compatible = "asahi-kasei,ak4613";
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#sound-dai-cells = <0>;
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reg = <0x10>;
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clocks = <&rcar_sound 0>; /* audio_clkout */
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asahi-kasei,in1-single-end;
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asahi-kasei,in2-single-end;
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asahi-kasei,out1-single-end;
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asahi-kasei,out2-single-end;
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asahi-kasei,out3-single-end;
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asahi-kasei,out4-single-end;
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asahi-kasei,out5-single-end;
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asahi-kasei,out6-single-end;
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port {
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ak4613_endpoint: endpoint {
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remote-endpoint = <&rsnd_for_ak4613>;
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};
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};
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};
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composite-in@20 {
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compatible = "adi,adv7180cp";
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reg = <0x20>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7180_in: endpoint {
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remote-endpoint = <&composite_con_in>;
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};
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};
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port@3 {
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reg = <3>;
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/*
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* The VIN4 video input path is shared between
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* CVBS and HDMI inputs through SW[49-53]
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* switches.
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*
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* CVBS is the default selection, link it to
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* VIN4 here.
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*/
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adv7180_out: endpoint {
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remote-endpoint = <&vin4_in>;
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};
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};
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};
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};
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hdmi-encoder@39 {
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compatible = "adi,adv7511w";
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reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
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reg-names = "main", "edid", "cec", "packet";
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interrupt-parent = <&gpio1>;
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interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
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adi,input-depth = <8>;
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7511_in: endpoint {
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remote-endpoint = <&thc63lvd1024_out>;
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};
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};
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port@1 {
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reg = <1>;
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adv7511_out: endpoint {
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remote-endpoint = <&hdmi_con_out>;
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};
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};
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};
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};
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hdmi-decoder@4c {
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compatible = "adi,adv7612";
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reg = <0x4c>;
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default-input = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7612_in: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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port@2 {
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reg = <2>;
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/*
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* The VIN4 video input path is shared between
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* CVBS and HDMI inputs through SW[49-53]
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* switches.
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*
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* CVBS is the default selection, leave HDMI
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* not connected here.
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*/
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adv7612_out: endpoint {
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pclk-sample = <0>;
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hsync-active = <0>;
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vsync-active = <0>;
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};
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};
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};
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};
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cs2000: clk-multiplier@4f {
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#clock-cells = <0>;
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compatible = "cirrus,cs2000-cp";
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reg = <0x4f>;
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clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
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clock-names = "clk_in", "ref_clk";
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assigned-clocks = <&cs2000>;
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assigned-clock-rates = <24576000>; /* 1/1 divide */
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};
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eeprom@50 {
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compatible = "rohm,br24t01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&lvds0 {
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status = "okay";
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clocks = <&cpg CPG_MOD 727>,
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<&x12_clk>,
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<&extal_clk>;
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clock-names = "fck", "dclkin.0", "extal";
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ports {
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port@1 {
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lvds0_out: endpoint {
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remote-endpoint = <&thc63lvd1024_in>;
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};
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};
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};
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};
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&lvds1 {
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/*
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* Even though the LVDS1 output is not connected, the encoder must be
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* enabled to supply a pixel clock to the DU for the DPAD output when
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* LVDS0 is in use.
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*/
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status = "okay";
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clocks = <&cpg CPG_MOD 727>,
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<&x12_clk>,
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<&extal_clk>;
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clock-names = "fck", "dclkin.0", "extal";
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};
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&ohci0 {
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dr_mode = "host";
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status = "okay";
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};
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&pfc {
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avb0_pins: avb {
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groups = "avb0_link", "avb0_mdio", "avb0_mii";
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function = "avb0";
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};
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can0_pins: can0 {
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groups = "can0_data_a";
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function = "can0";
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};
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can1_pins: can1 {
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groups = "can1_data_a";
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function = "can1";
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};
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du_pins: du {
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groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
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function = "du";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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keys_pins: keys {
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pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
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bias-pull-up;
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};
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pwm0_pins: pwm0 {
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groups = "pwm0_c";
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function = "pwm0";
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};
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pwm1_pins: pwm1 {
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groups = "pwm1_c";
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function = "pwm1";
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};
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rpc_pins: rpc {
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groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
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"rpc_int";
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function = "rpc";
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};
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scif2_pins: scif2 {
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groups = "scif2_data";
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function = "scif2";
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};
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sdhi2_pins: sd2 {
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groups = "mmc_data8", "mmc_ctrl";
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function = "mmc";
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power-source = <1800>;
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};
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sdhi2_pins_uhs: sd2_uhs {
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groups = "mmc_data8", "mmc_ctrl";
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function = "mmc";
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power-source = <1800>;
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};
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sound_pins: sound {
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groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
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function = "ssi";
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};
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sound_clk_pins: sound-clk {
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groups = "audio_clk_a", "audio_clk_b",
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"audio_clkout", "audio_clkout1";
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function = "audio_clk";
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};
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usb0_pins: usb0 {
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groups = "usb0";
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function = "usb0";
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};
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vin4_pins_cvbs: vin4 {
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groups = "vin4_data8", "vin4_sync", "vin4_clk";
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function = "vin4";
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};
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};
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&pwm0 {
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pinctrl-0 = <&pwm0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-0 = <&pwm1_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&rcar_sound {
|
|
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* Single DAI */
|
|
#sound-dai-cells = <0>;
|
|
|
|
/* audio_clkout0/1 */
|
|
#clock-cells = <1>;
|
|
clock-frequency = <12288000 11289600>;
|
|
|
|
status = "okay";
|
|
|
|
clocks = <&cpg CPG_MOD 1005>,
|
|
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
|
|
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
|
|
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
|
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
|
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
|
<&cs2000>, <&audio_clk_b>,
|
|
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
|
|
|
|
ports {
|
|
rsnd_port0: port {
|
|
rsnd_for_ak4613: endpoint {
|
|
remote-endpoint = <&ak4613_endpoint>;
|
|
dai-format = "left_j";
|
|
bitclock-master = <&rsnd_for_ak4613>;
|
|
frame-master = <&rsnd_for_ak4613>;
|
|
playback = <&ssi3>, <&src5>, <&dvc0>;
|
|
capture = <&ssi4>, <&src6>, <&dvc1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rpc {
|
|
pinctrl-0 = <&rpc_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* Left disabled. To be enabled by firmware when unlocked. */
|
|
|
|
flash@0 {
|
|
compatible = "cypress,hyperflash", "cfi-flash";
|
|
reg = <0>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
bootparam@0 {
|
|
reg = <0x00000000 0x040000>;
|
|
read-only;
|
|
};
|
|
bl2@40000 {
|
|
reg = <0x00040000 0x140000>;
|
|
read-only;
|
|
};
|
|
cert_header_sa6@180000 {
|
|
reg = <0x00180000 0x040000>;
|
|
read-only;
|
|
};
|
|
bl31@1c0000 {
|
|
reg = <0x001c0000 0x040000>;
|
|
read-only;
|
|
};
|
|
tee@200000 {
|
|
reg = <0x00200000 0x440000>;
|
|
read-only;
|
|
};
|
|
uboot@640000 {
|
|
reg = <0x00640000 0x100000>;
|
|
read-only;
|
|
};
|
|
dtb@740000 {
|
|
reg = <0x00740000 0x080000>;
|
|
};
|
|
kernel@7c0000 {
|
|
reg = <0x007c0000 0x1400000>;
|
|
};
|
|
user@1bc0000 {
|
|
reg = <0x01bc0000 0x2440000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rwdt {
|
|
timeout-sec = <60>;
|
|
status = "okay";
|
|
};
|
|
|
|
&scif2 {
|
|
pinctrl-0 = <&scif2_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&sdhi2 {
|
|
/* used for on-board eMMC */
|
|
pinctrl-0 = <&sdhi2_pins>;
|
|
pinctrl-1 = <&sdhi2_pins_uhs>;
|
|
pinctrl-names = "default", "state_uhs";
|
|
|
|
vmmc-supply = <®_3p3v>;
|
|
vqmmc-supply = <®_1p8v>;
|
|
bus-width = <8>;
|
|
mmc-hs200-1_8v;
|
|
no-sd;
|
|
no-sdio;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&ssi4 {
|
|
shared-pin;
|
|
};
|
|
|
|
&usb2_phy0 {
|
|
pinctrl-0 = <&usb0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
renesas,no-otg-pins;
|
|
status = "okay";
|
|
};
|
|
|
|
&vin4 {
|
|
pinctrl-0 = <&vin4_pins_cvbs>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
|
|
ports {
|
|
port {
|
|
vin4_in: endpoint {
|
|
remote-endpoint = <&adv7180_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|