1166 lines
28 KiB
C
1166 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DA8XX/OMAP L1XX platform device data
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*
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* Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
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* Derived from code that was:
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* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
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*/
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#include <linux/ahci_platform.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/dma-map-ops.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/serial_8250.h>
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#include "common.h"
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#include "cputype.h"
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#include "da8xx.h"
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#include "asp.h"
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#include "cpuidle.h"
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#include "irqs.h"
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#include "sram.h"
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#define DA8XX_TPCC_BASE 0x01c00000
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#define DA8XX_TPTC0_BASE 0x01c08000
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#define DA8XX_TPTC1_BASE 0x01c08400
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#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
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#define DA8XX_I2C0_BASE 0x01c22000
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#define DA8XX_RTC_BASE 0x01c23000
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#define DA8XX_PRUSS_MEM_BASE 0x01c30000
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#define DA8XX_MMCSD0_BASE 0x01c40000
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#define DA8XX_SPI0_BASE 0x01c41000
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#define DA830_SPI1_BASE 0x01e12000
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#define DA8XX_LCD_CNTRL_BASE 0x01e13000
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#define DA850_SATA_BASE 0x01e18000
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#define DA850_MMCSD1_BASE 0x01e1b000
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#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
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#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
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#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
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#define DA8XX_EMAC_MDIO_BASE 0x01e24000
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#define DA8XX_I2C1_BASE 0x01e28000
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#define DA850_TPCC1_BASE 0x01e30000
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#define DA850_TPTC2_BASE 0x01e38000
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#define DA850_SPI1_BASE 0x01f0e000
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#define DA8XX_DDR2_CTL_BASE 0xb0000000
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#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
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#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
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#define DA8XX_EMAC_RAM_OFFSET 0x0000
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#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
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void __iomem *da8xx_syscfg0_base;
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void __iomem *da8xx_syscfg1_base;
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static struct plat_serial8250_port da8xx_serial0_pdata[] = {
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{
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.mapbase = DA8XX_UART0_BASE,
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.irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM,
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.regshift = 2,
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},
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{
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.flags = 0,
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}
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};
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static struct plat_serial8250_port da8xx_serial1_pdata[] = {
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{
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.mapbase = DA8XX_UART1_BASE,
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.irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM,
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.regshift = 2,
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},
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{
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.flags = 0,
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}
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};
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static struct plat_serial8250_port da8xx_serial2_pdata[] = {
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{
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.mapbase = DA8XX_UART2_BASE,
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.irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM,
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.regshift = 2,
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},
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{
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.flags = 0,
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}
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};
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struct platform_device da8xx_serial_device[] = {
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{
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = da8xx_serial0_pdata,
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}
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},
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{
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM1,
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.dev = {
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.platform_data = da8xx_serial1_pdata,
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}
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},
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{
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM2,
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.dev = {
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.platform_data = da8xx_serial2_pdata,
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}
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},
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{
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}
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};
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static s8 da8xx_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{1, 7},
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{-1, -1}
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};
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static s8 da850_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{-1, -1}
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};
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static struct edma_soc_info da8xx_edma0_pdata = {
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.queue_priority_mapping = da8xx_queue_priority_mapping,
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.default_queue = EVENTQ_1,
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};
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static struct edma_soc_info da850_edma1_pdata = {
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.queue_priority_mapping = da850_queue_priority_mapping,
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.default_queue = EVENTQ_0,
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};
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static struct resource da8xx_edma0_resources[] = {
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{
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.name = "edma3_cc",
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.start = DA8XX_TPCC_BASE,
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.end = DA8XX_TPCC_BASE + SZ_32K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc0",
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.start = DA8XX_TPTC0_BASE,
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.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc1",
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.start = DA8XX_TPTC1_BASE,
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.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_ccint",
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma3_ccerrint",
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource da850_edma1_resources[] = {
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{
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.name = "edma3_cc",
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.start = DA850_TPCC1_BASE,
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.end = DA850_TPCC1_BASE + SZ_32K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc0",
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.start = DA850_TPTC2_BASE,
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.end = DA850_TPTC2_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_ccint",
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.start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma3_ccerrint",
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.start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
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.flags = IORESOURCE_IRQ,
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},
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};
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static const struct platform_device_info da8xx_edma0_device __initconst = {
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.name = "edma",
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.id = 0,
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.dma_mask = DMA_BIT_MASK(32),
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.res = da8xx_edma0_resources,
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.num_res = ARRAY_SIZE(da8xx_edma0_resources),
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.data = &da8xx_edma0_pdata,
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.size_data = sizeof(da8xx_edma0_pdata),
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};
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static const struct platform_device_info da850_edma1_device __initconst = {
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.name = "edma",
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.id = 1,
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.dma_mask = DMA_BIT_MASK(32),
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.res = da850_edma1_resources,
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.num_res = ARRAY_SIZE(da850_edma1_resources),
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.data = &da850_edma1_pdata,
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.size_data = sizeof(da850_edma1_pdata),
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};
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static const struct dma_slave_map da830_edma_map[] = {
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{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
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{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
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{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
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{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
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{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
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{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
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{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
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{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
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{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
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{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
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{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
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{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
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};
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int __init da830_register_edma(struct edma_rsv_info *rsv)
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{
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struct platform_device *edma_pdev;
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da8xx_edma0_pdata.rsv = rsv;
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da8xx_edma0_pdata.slave_map = da830_edma_map;
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da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
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edma_pdev = platform_device_register_full(&da8xx_edma0_device);
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return PTR_ERR_OR_ZERO(edma_pdev);
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}
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static const struct dma_slave_map da850_edma0_map[] = {
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{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
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{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
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{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
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{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
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{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
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{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
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{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
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{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
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{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
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{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
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{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
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{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
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};
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static const struct dma_slave_map da850_edma1_map[] = {
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{ "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
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{ "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
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};
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int __init da850_register_edma(struct edma_rsv_info *rsv[2])
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{
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struct platform_device *edma_pdev;
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if (rsv) {
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da8xx_edma0_pdata.rsv = rsv[0];
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da850_edma1_pdata.rsv = rsv[1];
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}
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da8xx_edma0_pdata.slave_map = da850_edma0_map;
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da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
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edma_pdev = platform_device_register_full(&da8xx_edma0_device);
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if (IS_ERR(edma_pdev)) {
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pr_warn("%s: Failed to register eDMA0\n", __func__);
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return PTR_ERR(edma_pdev);
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}
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da850_edma1_pdata.slave_map = da850_edma1_map;
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da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
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edma_pdev = platform_device_register_full(&da850_edma1_device);
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return PTR_ERR_OR_ZERO(edma_pdev);
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}
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static struct resource da8xx_i2c_resources0[] = {
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{
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.start = DA8XX_I2C0_BASE,
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.end = DA8XX_I2C0_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
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.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device da8xx_i2c_device0 = {
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.name = "i2c_davinci",
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.id = 1,
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.num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
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.resource = da8xx_i2c_resources0,
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};
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static struct resource da8xx_i2c_resources1[] = {
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{
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.start = DA8XX_I2C1_BASE,
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.end = DA8XX_I2C1_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
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.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device da8xx_i2c_device1 = {
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.name = "i2c_davinci",
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.id = 2,
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.num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
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.resource = da8xx_i2c_resources1,
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};
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int __init da8xx_register_i2c(int instance,
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struct davinci_i2c_platform_data *pdata)
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{
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struct platform_device *pdev;
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if (instance == 0)
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pdev = &da8xx_i2c_device0;
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else if (instance == 1)
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pdev = &da8xx_i2c_device1;
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else
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return -EINVAL;
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pdev->dev.platform_data = pdata;
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return platform_device_register(pdev);
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}
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static struct resource da8xx_watchdog_resources[] = {
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{
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.start = DA8XX_WDOG_BASE,
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.end = DA8XX_WDOG_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device da8xx_wdt_device = {
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.name = "davinci-wdt",
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.id = -1,
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.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
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.resource = da8xx_watchdog_resources,
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};
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int __init da8xx_register_watchdog(void)
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{
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return platform_device_register(&da8xx_wdt_device);
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}
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static struct resource da8xx_emac_resources[] = {
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{
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.start = DA8XX_EMAC_CPPI_PORT_BASE,
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.end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
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.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
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.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
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.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
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.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
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.flags = IORESOURCE_IRQ,
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},
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};
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struct emac_platform_data da8xx_emac_pdata = {
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.ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
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.ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
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.ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
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.ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
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.version = EMAC_VERSION_2,
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};
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static struct platform_device da8xx_emac_device = {
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.name = "davinci_emac",
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.id = 1,
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.dev = {
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.platform_data = &da8xx_emac_pdata,
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},
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.num_resources = ARRAY_SIZE(da8xx_emac_resources),
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.resource = da8xx_emac_resources,
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};
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static struct resource da8xx_mdio_resources[] = {
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{
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.start = DA8XX_EMAC_MDIO_BASE,
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.end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device da8xx_mdio_device = {
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.name = "davinci_mdio",
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.id = 0,
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.num_resources = ARRAY_SIZE(da8xx_mdio_resources),
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.resource = da8xx_mdio_resources,
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};
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int __init da8xx_register_emac(void)
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{
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int ret;
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ret = platform_device_register(&da8xx_mdio_device);
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if (ret < 0)
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return ret;
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return platform_device_register(&da8xx_emac_device);
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}
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static struct resource da830_mcasp1_resources[] = {
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{
|
|
.name = "mpu",
|
|
.start = DAVINCI_DA830_MCASP1_REG_BASE,
|
|
.end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
/* TX event */
|
|
{
|
|
.name = "tx",
|
|
.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
|
|
.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
/* RX event */
|
|
{
|
|
.name = "rx",
|
|
.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
|
|
.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{
|
|
.name = "common",
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da830_mcasp1_device = {
|
|
.name = "davinci-mcasp",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(da830_mcasp1_resources),
|
|
.resource = da830_mcasp1_resources,
|
|
};
|
|
|
|
static struct resource da830_mcasp2_resources[] = {
|
|
{
|
|
.name = "mpu",
|
|
.start = DAVINCI_DA830_MCASP2_REG_BASE,
|
|
.end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
/* TX event */
|
|
{
|
|
.name = "tx",
|
|
.start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
|
|
.end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
/* RX event */
|
|
{
|
|
.name = "rx",
|
|
.start = DAVINCI_DA830_DMA_MCASP2_AREVT,
|
|
.end = DAVINCI_DA830_DMA_MCASP2_AREVT,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{
|
|
.name = "common",
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da830_mcasp2_device = {
|
|
.name = "davinci-mcasp",
|
|
.id = 2,
|
|
.num_resources = ARRAY_SIZE(da830_mcasp2_resources),
|
|
.resource = da830_mcasp2_resources,
|
|
};
|
|
|
|
static struct resource da850_mcasp_resources[] = {
|
|
{
|
|
.name = "mpu",
|
|
.start = DAVINCI_DA8XX_MCASP0_REG_BASE,
|
|
.end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
/* TX event */
|
|
{
|
|
.name = "tx",
|
|
.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
|
|
.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
/* RX event */
|
|
{
|
|
.name = "rx",
|
|
.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
|
|
.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{
|
|
.name = "common",
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da850_mcasp_device = {
|
|
.name = "davinci-mcasp",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(da850_mcasp_resources),
|
|
.resource = da850_mcasp_resources,
|
|
};
|
|
|
|
void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
|
|
{
|
|
struct platform_device *pdev;
|
|
|
|
switch (id) {
|
|
case 0:
|
|
/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
|
|
pdev = &da850_mcasp_device;
|
|
break;
|
|
case 1:
|
|
/* Valid for DA830/OMAP-L137 only */
|
|
if (!cpu_is_davinci_da830())
|
|
return;
|
|
pdev = &da830_mcasp1_device;
|
|
break;
|
|
case 2:
|
|
/* Valid for DA830/OMAP-L137 only */
|
|
if (!cpu_is_davinci_da830())
|
|
return;
|
|
pdev = &da830_mcasp2_device;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
pdev->dev.platform_data = pdata;
|
|
platform_device_register(pdev);
|
|
}
|
|
|
|
static struct resource da8xx_pruss_resources[] = {
|
|
{
|
|
.start = DA8XX_PRUSS_MEM_BASE,
|
|
.end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
|
|
.pintc_base = 0x4000,
|
|
};
|
|
|
|
static struct platform_device da8xx_uio_pruss_dev = {
|
|
.name = "pruss_uio",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(da8xx_pruss_resources),
|
|
.resource = da8xx_pruss_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &da8xx_uio_pruss_pdata,
|
|
}
|
|
};
|
|
|
|
int __init da8xx_register_uio_pruss(void)
|
|
{
|
|
da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
|
|
return platform_device_register(&da8xx_uio_pruss_dev);
|
|
}
|
|
|
|
static struct lcd_ctrl_config lcd_cfg = {
|
|
.panel_shade = COLOR_ACTIVE,
|
|
.bpp = 16,
|
|
};
|
|
|
|
struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
|
|
.manu_name = "sharp",
|
|
.controller_data = &lcd_cfg,
|
|
.type = "Sharp_LCD035Q3DG01",
|
|
};
|
|
|
|
struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
|
|
.manu_name = "sharp",
|
|
.controller_data = &lcd_cfg,
|
|
.type = "Sharp_LK043T1DG01",
|
|
};
|
|
|
|
static struct resource da8xx_lcdc_resources[] = {
|
|
[0] = { /* registers */
|
|
.start = DA8XX_LCD_CNTRL_BASE,
|
|
.end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = { /* interrupt */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_lcdc_device = {
|
|
.name = "da8xx_lcdc",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
|
|
.resource = da8xx_lcdc_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
}
|
|
};
|
|
|
|
int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
|
|
{
|
|
da8xx_lcdc_device.dev.platform_data = pdata;
|
|
return platform_device_register(&da8xx_lcdc_device);
|
|
}
|
|
|
|
static struct resource da8xx_gpio_resources[] = {
|
|
{ /* registers */
|
|
.start = DA8XX_GPIO_BASE,
|
|
.end = DA8XX_GPIO_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* interrupt */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_gpio_device = {
|
|
.name = "davinci_gpio",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(da8xx_gpio_resources),
|
|
.resource = da8xx_gpio_resources,
|
|
};
|
|
|
|
int __init da8xx_register_gpio(void *pdata)
|
|
{
|
|
da8xx_gpio_device.dev.platform_data = pdata;
|
|
return platform_device_register(&da8xx_gpio_device);
|
|
}
|
|
|
|
static struct resource da8xx_mmcsd0_resources[] = {
|
|
{ /* registers */
|
|
.start = DA8XX_MMCSD0_BASE,
|
|
.end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* interrupt */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_mmcsd0_device = {
|
|
.name = "da830-mmc",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
|
|
.resource = da8xx_mmcsd0_resources,
|
|
};
|
|
|
|
int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
|
|
{
|
|
da8xx_mmcsd0_device.dev.platform_data = config;
|
|
return platform_device_register(&da8xx_mmcsd0_device);
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
|
static struct resource da850_mmcsd1_resources[] = {
|
|
{ /* registers */
|
|
.start = DA850_MMCSD1_BASE,
|
|
.end = DA850_MMCSD1_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* interrupt */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da850_mmcsd1_device = {
|
|
.name = "da830-mmc",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
|
|
.resource = da850_mmcsd1_resources,
|
|
};
|
|
|
|
int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
|
|
{
|
|
da850_mmcsd1_device.dev.platform_data = config;
|
|
return platform_device_register(&da850_mmcsd1_device);
|
|
}
|
|
#endif
|
|
|
|
static struct resource da8xx_rproc_resources[] = {
|
|
{ /* DSP boot address */
|
|
.name = "host1cfg",
|
|
.start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
|
|
.end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* DSP interrupt registers */
|
|
.name = "chipsig",
|
|
.start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
|
|
.end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* DSP L2 RAM */
|
|
.name = "l2sram",
|
|
.start = DA8XX_DSP_L2_RAM_BASE,
|
|
.end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* DSP L1P RAM */
|
|
.name = "l1pram",
|
|
.start = DA8XX_DSP_L1P_RAM_BASE,
|
|
.end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* DSP L1D RAM */
|
|
.name = "l1dram",
|
|
.start = DA8XX_DSP_L1D_RAM_BASE,
|
|
.end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* dsp irq */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_dsp = {
|
|
.name = "davinci-rproc",
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.num_resources = ARRAY_SIZE(da8xx_rproc_resources),
|
|
.resource = da8xx_rproc_resources,
|
|
};
|
|
|
|
static bool rproc_mem_inited __initdata;
|
|
|
|
#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
|
|
|
|
static phys_addr_t rproc_base __initdata;
|
|
static unsigned long rproc_size __initdata;
|
|
|
|
static int __init early_rproc_mem(char *p)
|
|
{
|
|
char *endp;
|
|
|
|
if (p == NULL)
|
|
return 0;
|
|
|
|
rproc_size = memparse(p, &endp);
|
|
if (*endp == '@')
|
|
rproc_base = memparse(endp + 1, NULL);
|
|
|
|
return 0;
|
|
}
|
|
early_param("rproc_mem", early_rproc_mem);
|
|
|
|
void __init da8xx_rproc_reserve_cma(void)
|
|
{
|
|
struct cma *cma;
|
|
int ret;
|
|
|
|
if (!rproc_base || !rproc_size) {
|
|
pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
|
|
" 'nn' and 'address' must both be non-zero\n",
|
|
__func__);
|
|
|
|
return;
|
|
}
|
|
|
|
pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
|
|
__func__, rproc_size, (unsigned long)rproc_base);
|
|
|
|
ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
|
|
true);
|
|
if (ret) {
|
|
pr_err("%s: dma_contiguous_reserve_area failed %d\n",
|
|
__func__, ret);
|
|
return;
|
|
}
|
|
da8xx_dsp.dev.cma_area = cma;
|
|
rproc_mem_inited = true;
|
|
}
|
|
#else
|
|
|
|
void __init da8xx_rproc_reserve_cma(void)
|
|
{
|
|
}
|
|
|
|
#endif
|
|
|
|
int __init da8xx_register_rproc(void)
|
|
{
|
|
int ret;
|
|
|
|
if (!rproc_mem_inited) {
|
|
pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
|
|
__func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = platform_device_register(&da8xx_dsp);
|
|
if (ret)
|
|
pr_err("%s: can't register DSP device: %d\n", __func__, ret);
|
|
|
|
return ret;
|
|
};
|
|
|
|
static struct resource da8xx_rtc_resources[] = {
|
|
{
|
|
.start = DA8XX_RTC_BASE,
|
|
.end = DA8XX_RTC_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* timer irq */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{ /* alarm irq */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_rtc_device = {
|
|
.name = "da830-rtc",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(da8xx_rtc_resources),
|
|
.resource = da8xx_rtc_resources,
|
|
};
|
|
|
|
int da8xx_register_rtc(void)
|
|
{
|
|
return platform_device_register(&da8xx_rtc_device);
|
|
}
|
|
|
|
static void __iomem *da8xx_ddr2_ctlr_base;
|
|
void __iomem * __init da8xx_get_mem_ctlr(void)
|
|
{
|
|
if (da8xx_ddr2_ctlr_base)
|
|
return da8xx_ddr2_ctlr_base;
|
|
|
|
da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
|
|
if (!da8xx_ddr2_ctlr_base)
|
|
pr_warn("%s: Unable to map DDR2 controller", __func__);
|
|
|
|
return da8xx_ddr2_ctlr_base;
|
|
}
|
|
|
|
static struct resource da8xx_cpuidle_resources[] = {
|
|
{
|
|
.start = DA8XX_DDR2_CTL_BASE,
|
|
.end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
/* DA8XX devices support DDR2 power down */
|
|
static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
|
|
.ddr2_pdown = 1,
|
|
};
|
|
|
|
|
|
static struct platform_device da8xx_cpuidle_device = {
|
|
.name = "cpuidle-davinci",
|
|
.num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
|
|
.resource = da8xx_cpuidle_resources,
|
|
.dev = {
|
|
.platform_data = &da8xx_cpuidle_pdata,
|
|
},
|
|
};
|
|
|
|
int __init da8xx_register_cpuidle(void)
|
|
{
|
|
da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
|
|
|
|
return platform_device_register(&da8xx_cpuidle_device);
|
|
}
|
|
|
|
static struct resource da8xx_spi0_resources[] = {
|
|
[0] = {
|
|
.start = DA8XX_SPI0_BASE,
|
|
.end = DA8XX_SPI0_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct resource da8xx_spi1_resources[] = {
|
|
[0] = {
|
|
.start = DA830_SPI1_BASE,
|
|
.end = DA830_SPI1_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
|
|
[0] = {
|
|
.version = SPI_VERSION_2,
|
|
.intr_line = 1,
|
|
.dma_event_q = EVENTQ_0,
|
|
.prescaler_limit = 2,
|
|
},
|
|
[1] = {
|
|
.version = SPI_VERSION_2,
|
|
.intr_line = 1,
|
|
.dma_event_q = EVENTQ_0,
|
|
.prescaler_limit = 2,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_spi_device[] = {
|
|
[0] = {
|
|
.name = "spi_davinci",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(da8xx_spi0_resources),
|
|
.resource = da8xx_spi0_resources,
|
|
.dev = {
|
|
.platform_data = &da8xx_spi_pdata[0],
|
|
},
|
|
},
|
|
[1] = {
|
|
.name = "spi_davinci",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(da8xx_spi1_resources),
|
|
.resource = da8xx_spi1_resources,
|
|
.dev = {
|
|
.platform_data = &da8xx_spi_pdata[1],
|
|
},
|
|
},
|
|
};
|
|
|
|
int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
|
|
{
|
|
if (instance < 0 || instance > 1)
|
|
return -EINVAL;
|
|
|
|
da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
|
|
|
|
if (instance == 1 && cpu_is_davinci_da850()) {
|
|
da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
|
|
da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
|
|
}
|
|
|
|
return platform_device_register(&da8xx_spi_device[instance]);
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
|
int __init da850_register_sata_refclk(int rate)
|
|
{
|
|
struct clk *clk;
|
|
|
|
clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
return clk_register_clkdev(clk, "refclk", "ahci_da850");
|
|
}
|
|
|
|
static struct resource da850_sata_resources[] = {
|
|
{
|
|
.start = DA850_SATA_BASE,
|
|
.end = DA850_SATA_BASE + 0x1fff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
|
|
.end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device da850_sata_device = {
|
|
.name = "ahci_da850",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &da850_sata_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.num_resources = ARRAY_SIZE(da850_sata_resources),
|
|
.resource = da850_sata_resources,
|
|
};
|
|
|
|
int __init da850_register_sata(unsigned long refclkpn)
|
|
{
|
|
int ret;
|
|
|
|
ret = da850_register_sata_refclk(refclkpn);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return platform_device_register(&da850_sata_device);
|
|
}
|
|
#endif
|
|
|
|
static struct regmap *da8xx_cfgchip;
|
|
|
|
static const struct regmap_config da8xx_cfgchip_config __initconst = {
|
|
.name = "cfgchip",
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
|
|
};
|
|
|
|
/**
|
|
* da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
|
|
*
|
|
* This is for use on non-DT boards only. For DT boards, use
|
|
* syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
|
|
*
|
|
* Returns: Pointer to the CFGCHIP regmap or negative error code.
|
|
*/
|
|
struct regmap * __init da8xx_get_cfgchip(void)
|
|
{
|
|
if (IS_ERR_OR_NULL(da8xx_cfgchip))
|
|
da8xx_cfgchip = regmap_init_mmio(NULL,
|
|
DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
|
|
&da8xx_cfgchip_config);
|
|
|
|
return da8xx_cfgchip;
|
|
}
|