340 lines
6.7 KiB
ArmAsm
340 lines
6.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions.
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*
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* Copyright (C) 2015 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.arch armv8-a
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.fpu crypto-neon-fp-armv8
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SHASH .req q0
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T1 .req q1
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XL .req q2
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XM .req q3
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XH .req q4
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IN1 .req q4
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SHASH_L .req d0
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SHASH_H .req d1
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T1_L .req d2
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T1_H .req d3
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XL_L .req d4
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XL_H .req d5
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XM_L .req d6
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XM_H .req d7
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XH_L .req d8
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t0l .req d10
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t0h .req d11
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t1l .req d12
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t1h .req d13
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t2l .req d14
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t2h .req d15
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t3l .req d16
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t3h .req d17
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t4l .req d18
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t4h .req d19
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t0q .req q5
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t1q .req q6
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t2q .req q7
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t3q .req q8
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t4q .req q9
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T2 .req q9
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s1l .req d20
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s1h .req d21
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s2l .req d22
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s2h .req d23
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s3l .req d24
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s3h .req d25
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s4l .req d26
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s4h .req d27
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MASK .req d28
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SHASH2_p8 .req d28
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k16 .req d29
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k32 .req d30
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k48 .req d31
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SHASH2_p64 .req d31
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HH .req q10
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HH3 .req q11
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HH4 .req q12
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HH34 .req q13
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HH_L .req d20
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HH_H .req d21
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HH3_L .req d22
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HH3_H .req d23
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HH4_L .req d24
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HH4_H .req d25
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HH34_L .req d26
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HH34_H .req d27
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SHASH2_H .req d29
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XL2 .req q5
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XM2 .req q6
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XH2 .req q7
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T3 .req q8
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XL2_L .req d10
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XL2_H .req d11
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XM2_L .req d12
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XM2_H .req d13
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T3_L .req d16
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T3_H .req d17
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.text
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.macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4
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vmull.p64 \rd, \rn, \rm
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.endm
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/*
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* This implementation of 64x64 -> 128 bit polynomial multiplication
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* using vmull.p8 instructions (8x8 -> 16) is taken from the paper
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* "Fast Software Polynomial Multiplication on ARM Processors Using
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* the NEON Engine" by Danilo Camara, Conrado Gouvea, Julio Lopez and
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* Ricardo Dahab (https://hal.inria.fr/hal-01506572)
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*
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* It has been slightly tweaked for in-order performance, and to allow
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* 'rq' to overlap with 'ad' or 'bd'.
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*/
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.macro __pmull_p8, rq, ad, bd, b1=t4l, b2=t3l, b3=t4l, b4=t3l
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vext.8 t0l, \ad, \ad, #1 @ A1
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.ifc \b1, t4l
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vext.8 t4l, \bd, \bd, #1 @ B1
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.endif
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vmull.p8 t0q, t0l, \bd @ F = A1*B
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vext.8 t1l, \ad, \ad, #2 @ A2
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vmull.p8 t4q, \ad, \b1 @ E = A*B1
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.ifc \b2, t3l
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vext.8 t3l, \bd, \bd, #2 @ B2
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.endif
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vmull.p8 t1q, t1l, \bd @ H = A2*B
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vext.8 t2l, \ad, \ad, #3 @ A3
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vmull.p8 t3q, \ad, \b2 @ G = A*B2
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veor t0q, t0q, t4q @ L = E + F
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.ifc \b3, t4l
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vext.8 t4l, \bd, \bd, #3 @ B3
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.endif
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vmull.p8 t2q, t2l, \bd @ J = A3*B
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veor t0l, t0l, t0h @ t0 = (L) (P0 + P1) << 8
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veor t1q, t1q, t3q @ M = G + H
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.ifc \b4, t3l
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vext.8 t3l, \bd, \bd, #4 @ B4
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.endif
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vmull.p8 t4q, \ad, \b3 @ I = A*B3
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veor t1l, t1l, t1h @ t1 = (M) (P2 + P3) << 16
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vmull.p8 t3q, \ad, \b4 @ K = A*B4
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vand t0h, t0h, k48
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vand t1h, t1h, k32
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veor t2q, t2q, t4q @ N = I + J
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veor t0l, t0l, t0h
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veor t1l, t1l, t1h
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veor t2l, t2l, t2h @ t2 = (N) (P4 + P5) << 24
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vand t2h, t2h, k16
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veor t3l, t3l, t3h @ t3 = (K) (P6 + P7) << 32
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vmov.i64 t3h, #0
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vext.8 t0q, t0q, t0q, #15
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veor t2l, t2l, t2h
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vext.8 t1q, t1q, t1q, #14
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vmull.p8 \rq, \ad, \bd @ D = A*B
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vext.8 t2q, t2q, t2q, #13
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vext.8 t3q, t3q, t3q, #12
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veor t0q, t0q, t1q
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veor t2q, t2q, t3q
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veor \rq, \rq, t0q
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veor \rq, \rq, t2q
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.endm
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//
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// PMULL (64x64->128) based reduction for CPUs that can do
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// it in a single instruction.
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//
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.macro __pmull_reduce_p64
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vmull.p64 T1, XL_L, MASK
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veor XH_L, XH_L, XM_H
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vext.8 T1, T1, T1, #8
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veor XL_H, XL_H, XM_L
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veor T1, T1, XL
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vmull.p64 XL, T1_H, MASK
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.endm
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//
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// Alternative reduction for CPUs that lack support for the
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// 64x64->128 PMULL instruction
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//
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.macro __pmull_reduce_p8
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veor XL_H, XL_H, XM_L
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veor XH_L, XH_L, XM_H
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vshl.i64 T1, XL, #57
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vshl.i64 T2, XL, #62
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veor T1, T1, T2
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vshl.i64 T2, XL, #63
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veor T1, T1, T2
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veor XL_H, XL_H, T1_L
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veor XH_L, XH_L, T1_H
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vshr.u64 T1, XL, #1
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veor XH, XH, XL
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veor XL, XL, T1
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vshr.u64 T1, T1, #6
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vshr.u64 XL, XL, #1
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.endm
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.macro ghash_update, pn
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vld1.64 {XL}, [r1]
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/* do the head block first, if supplied */
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ldr ip, [sp]
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teq ip, #0
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beq 0f
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vld1.64 {T1}, [ip]
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teq r0, #0
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b 3f
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0: .ifc \pn, p64
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tst r0, #3 // skip until #blocks is a
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bne 2f // round multiple of 4
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vld1.8 {XL2-XM2}, [r2]!
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1: vld1.8 {T3-T2}, [r2]!
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vrev64.8 XL2, XL2
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vrev64.8 XM2, XM2
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subs r0, r0, #4
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vext.8 T1, XL2, XL2, #8
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veor XL2_H, XL2_H, XL_L
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veor XL, XL, T1
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vrev64.8 T3, T3
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vrev64.8 T1, T2
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vmull.p64 XH, HH4_H, XL_H // a1 * b1
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veor XL2_H, XL2_H, XL_H
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vmull.p64 XL, HH4_L, XL_L // a0 * b0
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vmull.p64 XM, HH34_H, XL2_H // (a1 + a0)(b1 + b0)
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vmull.p64 XH2, HH3_H, XM2_L // a1 * b1
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veor XM2_L, XM2_L, XM2_H
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vmull.p64 XL2, HH3_L, XM2_H // a0 * b0
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vmull.p64 XM2, HH34_L, XM2_L // (a1 + a0)(b1 + b0)
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veor XH, XH, XH2
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veor XL, XL, XL2
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veor XM, XM, XM2
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vmull.p64 XH2, HH_H, T3_L // a1 * b1
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veor T3_L, T3_L, T3_H
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vmull.p64 XL2, HH_L, T3_H // a0 * b0
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vmull.p64 XM2, SHASH2_H, T3_L // (a1 + a0)(b1 + b0)
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veor XH, XH, XH2
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veor XL, XL, XL2
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veor XM, XM, XM2
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vmull.p64 XH2, SHASH_H, T1_L // a1 * b1
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veor T1_L, T1_L, T1_H
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vmull.p64 XL2, SHASH_L, T1_H // a0 * b0
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vmull.p64 XM2, SHASH2_p64, T1_L // (a1 + a0)(b1 + b0)
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veor XH, XH, XH2
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veor XL, XL, XL2
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veor XM, XM, XM2
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beq 4f
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vld1.8 {XL2-XM2}, [r2]!
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veor T1, XL, XH
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veor XM, XM, T1
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__pmull_reduce_p64
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veor T1, T1, XH
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veor XL, XL, T1
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b 1b
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.endif
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2: vld1.64 {T1}, [r2]!
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subs r0, r0, #1
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3: /* multiply XL by SHASH in GF(2^128) */
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#ifndef CONFIG_CPU_BIG_ENDIAN
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vrev64.8 T1, T1
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#endif
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vext.8 IN1, T1, T1, #8
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veor T1_L, T1_L, XL_H
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veor XL, XL, IN1
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__pmull_\pn XH, XL_H, SHASH_H, s1h, s2h, s3h, s4h @ a1 * b1
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veor T1, T1, XL
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__pmull_\pn XL, XL_L, SHASH_L, s1l, s2l, s3l, s4l @ a0 * b0
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__pmull_\pn XM, T1_L, SHASH2_\pn @ (a1+a0)(b1+b0)
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4: veor T1, XL, XH
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veor XM, XM, T1
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__pmull_reduce_\pn
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veor T1, T1, XH
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veor XL, XL, T1
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bne 0b
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vst1.64 {XL}, [r1]
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bx lr
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.endm
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/*
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* void pmull_ghash_update(int blocks, u64 dg[], const char *src,
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* struct ghash_key const *k, const char *head)
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*/
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ENTRY(pmull_ghash_update_p64)
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vld1.64 {SHASH}, [r3]!
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vld1.64 {HH}, [r3]!
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vld1.64 {HH3-HH4}, [r3]
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veor SHASH2_p64, SHASH_L, SHASH_H
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veor SHASH2_H, HH_L, HH_H
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veor HH34_L, HH3_L, HH3_H
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veor HH34_H, HH4_L, HH4_H
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vmov.i8 MASK, #0xe1
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vshl.u64 MASK, MASK, #57
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ghash_update p64
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ENDPROC(pmull_ghash_update_p64)
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ENTRY(pmull_ghash_update_p8)
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vld1.64 {SHASH}, [r3]
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veor SHASH2_p8, SHASH_L, SHASH_H
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vext.8 s1l, SHASH_L, SHASH_L, #1
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vext.8 s2l, SHASH_L, SHASH_L, #2
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vext.8 s3l, SHASH_L, SHASH_L, #3
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vext.8 s4l, SHASH_L, SHASH_L, #4
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vext.8 s1h, SHASH_H, SHASH_H, #1
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vext.8 s2h, SHASH_H, SHASH_H, #2
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vext.8 s3h, SHASH_H, SHASH_H, #3
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vext.8 s4h, SHASH_H, SHASH_H, #4
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vmov.i64 k16, #0xffff
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vmov.i64 k32, #0xffffffff
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vmov.i64 k48, #0xffffffffffff
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ghash_update p8
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ENDPROC(pmull_ghash_update_p8)
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