125 lines
2.5 KiB
YAML
125 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Adreno/Snapdragon MDP4 display controller
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description: >
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MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
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maintainers:
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- Rob Clark <robdclark@gmail.com>
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properties:
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compatible:
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const: qcom,mdp4
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: core_clk
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- const: iface_clk
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- const: bus_clk
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- const: lut_clk
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- const: hdmi_clk
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- const: tv_clk
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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iommus:
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maxItems: 4
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: LCDC/LVDS
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: DSI1 Cmd / Video
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: DSI2 Cmd / Video
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port@3:
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$ref: /schemas/graph.yaml#/properties/port
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description: Digital TV
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qcom,lcdc-align-lsb:
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type: boolean
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description: >
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Indication that LSB alignment should be used for LCDC.
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This is only valid for 18bpp panels.
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required:
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- compatible
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- reg
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- clocks
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- ports
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additionalProperties: false
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examples:
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- |
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mdp: mdp@5100000 {
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compatible = "qcom,mdp4";
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reg = <0x05100000 0xf0000>;
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interrupts = <0 75 0>;
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clock-names =
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"core_clk",
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"iface_clk",
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"bus_clk",
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"lut_clk",
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"hdmi_clk",
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"tv_clk";
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clocks =
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<&mmcc 77>,
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<&mmcc 86>,
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<&mmcc 102>,
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<&mmcc 75>,
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<&mmcc 97>,
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<&mmcc 12>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdp_lvds_out: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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mdp_dsi1_out: endpoint {
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};
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};
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port@2 {
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reg = <2>;
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mdp_dsi2_out: endpoint {
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};
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};
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port@3 {
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reg = <3>;
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mdp_dtv_out: endpoint {
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remote-endpoint = <&hdmi_in>;
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};
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};
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};
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};
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