458 lines
18 KiB
C
458 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2011 - NVIDIA, Inc.
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*
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* Based on code copyright/by:
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* Copyright (c) 2008-2009, NVIDIA Corporation
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*/
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#ifndef __TEGRA20_SPDIF_H__
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#define __TEGRA20_SPDIF_H__
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#include "tegra_pcm.h"
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/* Offsets from TEGRA20_SPDIF_BASE */
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#define TEGRA20_SPDIF_CTRL 0x0
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#define TEGRA20_SPDIF_STATUS 0x4
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#define TEGRA20_SPDIF_STROBE_CTRL 0x8
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#define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C
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#define TEGRA20_SPDIF_DATA_OUT 0x40
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#define TEGRA20_SPDIF_DATA_IN 0x80
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#define TEGRA20_SPDIF_CH_STA_RX_A 0x100
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#define TEGRA20_SPDIF_CH_STA_RX_B 0x104
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#define TEGRA20_SPDIF_CH_STA_RX_C 0x108
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#define TEGRA20_SPDIF_CH_STA_RX_D 0x10C
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#define TEGRA20_SPDIF_CH_STA_RX_E 0x110
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#define TEGRA20_SPDIF_CH_STA_RX_F 0x114
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#define TEGRA20_SPDIF_CH_STA_TX_A 0x140
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#define TEGRA20_SPDIF_CH_STA_TX_B 0x144
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#define TEGRA20_SPDIF_CH_STA_TX_C 0x148
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#define TEGRA20_SPDIF_CH_STA_TX_D 0x14C
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#define TEGRA20_SPDIF_CH_STA_TX_E 0x150
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#define TEGRA20_SPDIF_CH_STA_TX_F 0x154
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#define TEGRA20_SPDIF_USR_STA_RX_A 0x180
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#define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0
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/* Fields in TEGRA20_SPDIF_CTRL */
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/* Start capturing from 0=right, 1=left channel */
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#define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30)
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/* SPDIF receiver(RX) enable */
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#define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29)
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/* SPDIF Transmitter(TX) enable */
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#define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28)
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/* Transmit Channel status */
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#define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27)
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/* Transmit user Data */
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#define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26)
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/* Interrupt on transmit error */
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#define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25)
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/* Interrupt on receive error */
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#define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24)
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/* Interrupt on invalid preamble */
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#define TEGRA20_SPDIF_CTRL_IE_P (1 << 23)
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/* Interrupt on "B" preamble */
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#define TEGRA20_SPDIF_CTRL_IE_B (1 << 22)
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/* Interrupt when block of channel status received */
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#define TEGRA20_SPDIF_CTRL_IE_C (1 << 21)
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/* Interrupt when a valid information unit (IU) is received */
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#define TEGRA20_SPDIF_CTRL_IE_U (1 << 20)
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/* Interrupt when RX user FIFO attention level is reached */
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#define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19)
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/* Interrupt when TX user FIFO attention level is reached */
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#define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18)
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/* Interrupt when RX data FIFO attention level is reached */
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#define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17)
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/* Interrupt when TX data FIFO attention level is reached */
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#define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16)
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/* Loopback test mode enable */
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#define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15)
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/*
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* Pack data mode:
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* 0 = Single data (16 bit needs to be padded to match the
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* interface data bit size).
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* 1 = Packeted left/right channel data into a single word.
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*/
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#define TEGRA20_SPDIF_CTRL_PACK (1 << 14)
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/*
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* 00 = 16bit data
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* 01 = 20bit data
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* 10 = 24bit data
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* 11 = raw data
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*/
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#define TEGRA20_SPDIF_BIT_MODE_16BIT 0
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#define TEGRA20_SPDIF_BIT_MODE_20BIT 1
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#define TEGRA20_SPDIF_BIT_MODE_24BIT 2
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#define TEGRA20_SPDIF_BIT_MODE_RAW 3
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#define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12
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#define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
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#define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT)
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/* Fields in TEGRA20_SPDIF_STATUS */
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/*
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* Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must
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* write a 1 to the corresponding bit location to clear the status.
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*/
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/*
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* Receiver(RX) shifter is busy receiving data.
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* This bit is asserted when the receiver first locked onto the
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* preamble of the data stream after RX_EN is asserted. This bit is
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* deasserted when either,
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* (a) the end of a frame is reached after RX_EN is deeasserted, or
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* (b) the SPDIF data stream becomes inactive.
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*/
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#define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29)
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/*
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* Transmitter(TX) shifter is busy transmitting data.
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* This bit is asserted when TX_EN is asserted.
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* This bit is deasserted when the end of a frame is reached after
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* TX_EN is deasserted.
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*/
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#define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28)
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/*
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* TX is busy shifting out channel status.
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* This bit is asserted when both TX_EN and TC_EN are asserted and
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* data from CH_STA_TX_A register is loaded into the internal shifter.
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* This bit is deasserted when either,
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* (a) the end of a frame is reached after TX_EN is deasserted, or
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* (b) CH_STA_TX_F register is loaded into the internal shifter.
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*/
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#define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27)
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/*
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* TX User data FIFO busy.
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* This bit is asserted when TX_EN and TXU_EN are asserted and
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* there's data in the TX user FIFO. This bit is deassert when either,
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* (a) the end of a frame is reached after TX_EN is deasserted, or
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* (b) there's no data left in the TX user FIFO.
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*/
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#define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26)
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/* TX FIFO Underrun error status */
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#define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25)
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/* RX FIFO Overrun error status */
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#define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24)
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/* Preamble status: 0=Preamble OK, 1=bad/missing preamble */
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#define TEGRA20_SPDIF_STATUS_IS_P (1 << 23)
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/* B-preamble detection status: 0=not detected, 1=B-preamble detected */
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#define TEGRA20_SPDIF_STATUS_IS_B (1 << 22)
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/*
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* RX channel block data receive status:
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* 0=entire block not recieved yet.
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* 1=received entire block of channel status,
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*/
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#define TEGRA20_SPDIF_STATUS_IS_C (1 << 21)
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/* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
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#define TEGRA20_SPDIF_STATUS_IS_U (1 << 20)
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/*
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* RX User FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19)
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/*
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* TX User FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18)
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/*
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* RX Data FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17)
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/*
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* TX Data FIFO Status:
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* 1=attention level reached, 0=attention level not reached.
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*/
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#define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16)
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/* Fields in TEGRA20_SPDIF_STROBE_CTRL */
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/*
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* Indicates the approximate number of detected SPDIFIN clocks within a
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* bi-phase period.
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*/
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#define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16
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#define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
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/* Data strobe mode: 0=Auto-locked 1=Manual locked */
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#define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15)
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/*
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* Manual data strobe time within the bi-phase clock period (in terms of
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* the number of over-sampling clocks).
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*/
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#define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8
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#define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
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/*
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* Manual SPDIFIN bi-phase clock period (in terms of the number of
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* over-sampling clocks).
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*/
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#define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
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#define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
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/* Fields in SPDIF_DATA_FIFO_CSR */
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/* Clear Receiver User FIFO (RX USR.FIFO) */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31)
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3
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/* RU FIFO attention level */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \
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(0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
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/* Number of RX USR.FIFO levels with valid data. */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT)
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/* Clear Transmitter User FIFO (TX USR.FIFO) */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23)
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/* TU FIFO attention level */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \
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(0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
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/* Number of TX USR.FIFO levels that could be filled. */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT)
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/* Clear Receiver Data FIFO (RX DATA.FIFO) */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15)
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2
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#define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3
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/* RU FIFO attention level */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \
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(0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
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/* Number of RX DATA.FIFO levels with valid data. */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT)
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/* Clear Transmitter Data FIFO (TX DATA.FIFO) */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7)
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/* TU FIFO attention level */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \
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(0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \
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(TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
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/* Number of TX DATA.FIFO levels that could be filled. */
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0
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#define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT)
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/* Fields in TEGRA20_SPDIF_DATA_OUT */
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/*
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* This register has 5 different formats:
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* 16-bit (BIT_MODE=00, PACK=0)
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* 20-bit (BIT_MODE=01, PACK=0)
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* 24-bit (BIT_MODE=10, PACK=0)
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* raw (BIT_MODE=11, PACK=0)
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* 16-bit packed (BIT_MODE=00, PACK=1)
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*/
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#define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0
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#define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0
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#define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0
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#define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0
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#define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16
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#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT)
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#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0
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#define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT)
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/* Fields in TEGRA20_SPDIF_DATA_IN */
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/*
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* This register has 5 different formats:
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* 16-bit (BIT_MODE=00, PACK=0)
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* 20-bit (BIT_MODE=01, PACK=0)
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* 24-bit (BIT_MODE=10, PACK=0)
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* raw (BIT_MODE=11, PACK=0)
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* 16-bit packed (BIT_MODE=00, PACK=1)
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*
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* Bits 31:24 are common to all modes except 16-bit packed
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*/
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#define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31)
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#define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30)
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#define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29)
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#define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28)
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#define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24
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#define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0
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#define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0
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#define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0
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#define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8
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#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4
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#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0
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#define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16
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#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT)
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#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0
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#define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT)
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/* Fields in TEGRA20_SPDIF_CH_STA_RX_A */
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/* Fields in TEGRA20_SPDIF_CH_STA_RX_B */
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/* Fields in TEGRA20_SPDIF_CH_STA_RX_C */
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/* Fields in TEGRA20_SPDIF_CH_STA_RX_D */
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/* Fields in TEGRA20_SPDIF_CH_STA_RX_E */
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/* Fields in TEGRA20_SPDIF_CH_STA_RX_F */
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/*
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* The 6-word receive channel data page buffer holds a block (192 frames) of
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* channel status information. The order of receive is from LSB to MSB
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* bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
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*/
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/* Fields in TEGRA20_SPDIF_CH_STA_TX_A */
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/* Fields in TEGRA20_SPDIF_CH_STA_TX_B */
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/* Fields in TEGRA20_SPDIF_CH_STA_TX_C */
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/* Fields in TEGRA20_SPDIF_CH_STA_TX_D */
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/* Fields in TEGRA20_SPDIF_CH_STA_TX_E */
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/* Fields in TEGRA20_SPDIF_CH_STA_TX_F */
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/*
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* The 6-word transmit channel data page buffer holds a block (192 frames) of
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* channel status information. The order of transmission is from LSB to MSB
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* bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A.
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*/
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/* Fields in TEGRA20_SPDIF_USR_STA_RX_A */
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/*
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* This 4-word deep FIFO receives user FIFO field information. The order of
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* receive is from LSB to MSB bit.
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*/
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/* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */
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/*
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* This 4-word deep FIFO transmits user FIFO field information. The order of
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* transmission is from LSB to MSB bit.
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*/
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struct tegra20_spdif {
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struct clk *clk_spdif_out;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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struct regmap *regmap;
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struct reset_control *reset;
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};
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#endif
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