510 lines
15 KiB
C
510 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel ThunderBay eMMC PHY driver
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*
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* Copyright (C) 2021 Intel Corporation
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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/* eMMC/SD/SDIO core/phy configuration registers */
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#define CTRL_CFG_0 0x00
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#define CTRL_CFG_1 0x04
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#define CTRL_PRESET_0 0x08
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#define CTRL_PRESET_1 0x0c
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#define CTRL_PRESET_2 0x10
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#define CTRL_PRESET_3 0x14
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#define CTRL_PRESET_4 0x18
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#define CTRL_CFG_2 0x1c
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#define CTRL_CFG_3 0x20
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#define PHY_CFG_0 0x24
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#define PHY_CFG_1 0x28
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#define PHY_CFG_2 0x2c
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#define PHYBIST_CTRL 0x30
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#define SDHC_STAT3 0x34
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#define PHY_STAT 0x38
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#define PHYBIST_STAT_0 0x3c
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#define PHYBIST_STAT_1 0x40
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#define EMMC_AXI 0x44
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/* CTRL_PRESET_3 */
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#define CTRL_PRESET3_MASK GENMASK(31, 0)
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#define CTRL_PRESET3_SHIFT 0
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/* CTRL_CFG_0 bit fields */
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#define SUPPORT_HS_MASK BIT(26)
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#define SUPPORT_HS_SHIFT 26
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#define SUPPORT_8B_MASK BIT(24)
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#define SUPPORT_8B_SHIFT 24
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/* CTRL_CFG_1 bit fields */
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#define SUPPORT_SDR50_MASK BIT(28)
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#define SUPPORT_SDR50_SHIFT 28
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#define SLOT_TYPE_MASK GENMASK(27, 26)
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#define SLOT_TYPE_OFFSET 26
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#define SUPPORT_64B_MASK BIT(24)
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#define SUPPORT_64B_SHIFT 24
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#define SUPPORT_HS400_MASK BIT(2)
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#define SUPPORT_HS400_SHIFT 2
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#define SUPPORT_DDR50_MASK BIT(1)
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#define SUPPORT_DDR50_SHIFT 1
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#define SUPPORT_SDR104_MASK BIT(0)
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#define SUPPORT_SDR104_SHIFT 0
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/* PHY_CFG_0 bit fields */
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#define SEL_DLY_TXCLK_MASK BIT(29)
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#define SEL_DLY_TXCLK_SHIFT 29
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#define SEL_DLY_RXCLK_MASK BIT(28)
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#define SEL_DLY_RXCLK_SHIFT 28
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#define OTAP_DLY_ENA_MASK BIT(27)
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#define OTAP_DLY_ENA_SHIFT 27
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#define OTAP_DLY_SEL_MASK GENMASK(26, 23)
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#define OTAP_DLY_SEL_SHIFT 23
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#define ITAP_CHG_WIN_MASK BIT(22)
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#define ITAP_CHG_WIN_SHIFT 22
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#define ITAP_DLY_ENA_MASK BIT(21)
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#define ITAP_DLY_ENA_SHIFT 21
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#define ITAP_DLY_SEL_MASK GENMASK(20, 16)
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#define ITAP_DLY_SEL_SHIFT 16
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#define RET_ENB_MASK BIT(15)
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#define RET_ENB_SHIFT 15
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#define RET_EN_MASK BIT(14)
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#define RET_EN_SHIFT 14
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#define DLL_IFF_MASK GENMASK(13, 11)
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#define DLL_IFF_SHIFT 11
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#define DLL_EN_MASK BIT(10)
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#define DLL_EN_SHIFT 10
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#define DLL_TRIM_ICP_MASK GENMASK(9, 6)
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#define DLL_TRIM_ICP_SHIFT 6
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#define RETRIM_EN_MASK BIT(5)
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#define RETRIM_EN_SHIFT 5
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#define RETRIM_MASK BIT(4)
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#define RETRIM_SHIFT 4
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#define DR_TY_MASK GENMASK(3, 1)
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#define DR_TY_SHIFT 1
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#define PWR_DOWN_MASK BIT(0)
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#define PWR_DOWN_SHIFT 0
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/* PHY_CFG_1 bit fields */
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#define REN_DAT_MASK GENMASK(19, 12)
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#define REN_DAT_SHIFT 12
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#define REN_CMD_MASK BIT(11)
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#define REN_CMD_SHIFT 11
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#define REN_STRB_MASK BIT(10)
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#define REN_STRB_SHIFT 10
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#define PU_STRB_MASK BIT(20)
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#define PU_STRB_SHIFT 20
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/* PHY_CFG_2 bit fields */
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#define CLKBUF_MASK GENMASK(24, 21)
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#define CLKBUF_SHIFT 21
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#define SEL_STRB_MASK GENMASK(20, 13)
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#define SEL_STRB_SHIFT 13
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#define SEL_FREQ_MASK GENMASK(12, 10)
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#define SEL_FREQ_SHIFT 10
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/* PHY_STAT bit fields */
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#define CAL_DONE BIT(6)
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#define DLL_RDY BIT(5)
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#define OTAP_DLY 0x0
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#define ITAP_DLY 0x0
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#define STRB 0x33
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/* From ACS_eMMC51_16nFFC_RO1100_Userguide_v1p0.pdf p17 */
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#define FREQSEL_200M_170M 0x0
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#define FREQSEL_170M_140M 0x1
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#define FREQSEL_140M_110M 0x2
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#define FREQSEL_110M_80M 0x3
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#define FREQSEL_80M_50M 0x4
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#define FREQSEL_275M_250M 0x5
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#define FREQSEL_250M_225M 0x6
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#define FREQSEL_225M_200M 0x7
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/* Phy power status */
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#define PHY_UNINITIALIZED 0
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#define PHY_INITIALIZED 1
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/*
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* During init(400KHz) phy_settings will be called with 200MHZ clock
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* To avoid incorrectly setting the phy for init(400KHZ) "phy_power_sts" is used.
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* When actual clock is set always phy is powered off once and then powered on.
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* (sdhci_arasan_set_clock). That feature will be used to identify whether the
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* settings are for init phy_power_on or actual clock phy_power_on
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* 0 --> init settings
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* 1 --> actual settings
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*/
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struct thunderbay_emmc_phy {
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void __iomem *reg_base;
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struct clk *emmcclk;
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int phy_power_sts;
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};
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static inline void update_reg(struct thunderbay_emmc_phy *tbh_phy, u32 offset,
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u32 mask, u32 shift, u32 val)
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{
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u32 tmp;
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tmp = readl(tbh_phy->reg_base + offset);
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tmp &= ~mask;
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tmp |= val << shift;
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writel(tmp, tbh_phy->reg_base + offset);
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}
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static int thunderbay_emmc_phy_power(struct phy *phy, bool power_on)
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{
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struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
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unsigned int freqsel = FREQSEL_200M_170M;
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unsigned long rate;
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static int lock;
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u32 val;
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int ret;
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/* Disable DLL */
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rate = clk_get_rate(tbh_phy->emmcclk);
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switch (rate) {
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case 200000000:
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/* lock dll only when it is used, i.e only if SEL_DLY_TXCLK/RXCLK are 0 */
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update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x0);
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break;
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/* dll lock not required for other frequencies */
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case 50000000 ... 52000000:
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case 400000:
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default:
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break;
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}
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if (!power_on)
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return 0;
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rate = clk_get_rate(tbh_phy->emmcclk);
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switch (rate) {
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case 170000001 ... 200000000:
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freqsel = FREQSEL_200M_170M;
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break;
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case 140000001 ... 170000000:
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freqsel = FREQSEL_170M_140M;
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break;
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case 110000001 ... 140000000:
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freqsel = FREQSEL_140M_110M;
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break;
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case 80000001 ... 110000000:
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freqsel = FREQSEL_110M_80M;
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break;
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case 50000000 ... 80000000:
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freqsel = FREQSEL_80M_50M;
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break;
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case 250000001 ... 275000000:
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freqsel = FREQSEL_275M_250M;
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break;
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case 225000001 ... 250000000:
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freqsel = FREQSEL_250M_225M;
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break;
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case 200000001 ... 225000000:
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freqsel = FREQSEL_225M_200M;
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break;
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default:
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break;
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}
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/* Clock rate is checked against upper limit. It may fall low during init */
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if (rate > 200000000)
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dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
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udelay(5);
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if (lock == 0) {
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/* PDB will be done only once per boot */
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update_reg(tbh_phy, PHY_CFG_0, PWR_DOWN_MASK,
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PWR_DOWN_SHIFT, 0x1);
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lock = 1;
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/*
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* According to the user manual, it asks driver to wait 5us for
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* calpad busy trimming. However it is documented that this value is
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* PVT(A.K.A. process, voltage and temperature) relevant, so some
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* failure cases are found which indicates we should be more tolerant
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* to calpad busy trimming.
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*/
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ret = readl_poll_timeout(tbh_phy->reg_base + PHY_STAT,
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val, (val & CAL_DONE), 10, 50);
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if (ret) {
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dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
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return ret;
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}
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}
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rate = clk_get_rate(tbh_phy->emmcclk);
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switch (rate) {
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case 200000000:
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/* Set frequency of the DLL operation */
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update_reg(tbh_phy, PHY_CFG_2, SEL_FREQ_MASK, SEL_FREQ_SHIFT, freqsel);
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/* Enable DLL */
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update_reg(tbh_phy, PHY_CFG_0, DLL_EN_MASK, DLL_EN_SHIFT, 0x1);
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/*
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* After enabling analog DLL circuits docs say that we need 10.2 us if
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* our source clock is at 50 MHz and that lock time scales linearly
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* with clock speed. If we are powering on the PHY and the card clock
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* is super slow (like 100kHz) this could take as long as 5.1 ms as
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* per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
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* hopefully we won't be running at 100 kHz, but we should still make
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* sure we wait long enough.
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*
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* NOTE: There appear to be corner cases where the DLL seems to take
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* extra long to lock for reasons that aren't understood. In some
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* extreme cases we've seen it take up to over 10ms (!). We'll be
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* generous and give it 50ms.
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*/
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ret = readl_poll_timeout(tbh_phy->reg_base + PHY_STAT,
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val, (val & DLL_RDY), 10, 50 * USEC_PER_MSEC);
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if (ret) {
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dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
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return ret;
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}
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break;
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default:
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break;
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}
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return 0;
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}
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static int thunderbay_emmc_phy_init(struct phy *phy)
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{
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struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
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tbh_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
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return PTR_ERR_OR_ZERO(tbh_phy->emmcclk);
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}
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static int thunderbay_emmc_phy_exit(struct phy *phy)
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{
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struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
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clk_put(tbh_phy->emmcclk);
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return 0;
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}
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static int thunderbay_emmc_phy_power_on(struct phy *phy)
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{
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struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
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unsigned long rate;
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/* Overwrite capability bits configurable in bootloader */
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update_reg(tbh_phy, CTRL_CFG_0,
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SUPPORT_HS_MASK, SUPPORT_HS_SHIFT, 0x1);
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update_reg(tbh_phy, CTRL_CFG_0,
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SUPPORT_8B_MASK, SUPPORT_8B_SHIFT, 0x1);
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update_reg(tbh_phy, CTRL_CFG_1,
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SUPPORT_SDR50_MASK, SUPPORT_SDR50_SHIFT, 0x1);
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update_reg(tbh_phy, CTRL_CFG_1,
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SUPPORT_DDR50_MASK, SUPPORT_DDR50_SHIFT, 0x1);
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update_reg(tbh_phy, CTRL_CFG_1,
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SUPPORT_SDR104_MASK, SUPPORT_SDR104_SHIFT, 0x1);
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update_reg(tbh_phy, CTRL_CFG_1,
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SUPPORT_HS400_MASK, SUPPORT_HS400_SHIFT, 0x1);
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update_reg(tbh_phy, CTRL_CFG_1,
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SUPPORT_64B_MASK, SUPPORT_64B_SHIFT, 0x1);
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if (tbh_phy->phy_power_sts == PHY_UNINITIALIZED) {
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/* Indicates initialization, settings for init, same as 400KHZ setting */
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK, SEL_DLY_TXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK, SEL_DLY_RXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK, ITAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK, ITAP_DLY_SEL_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK, OTAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK, OTAP_DLY_SEL_SHIFT, 0);
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update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK, DLL_TRIM_ICP_SHIFT, 0);
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update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
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} else if (tbh_phy->phy_power_sts == PHY_INITIALIZED) {
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/* Indicates actual clock setting */
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rate = clk_get_rate(tbh_phy->emmcclk);
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switch (rate) {
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case 200000000:
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
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SEL_DLY_TXCLK_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
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SEL_DLY_RXCLK_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
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ITAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
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ITAP_DLY_SEL_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
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OTAP_DLY_ENA_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
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OTAP_DLY_SEL_SHIFT, 2);
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update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
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DLL_TRIM_ICP_SHIFT, 0x8);
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update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
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DR_TY_SHIFT, 0x1);
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/* For HS400 only */
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update_reg(tbh_phy, PHY_CFG_2, SEL_STRB_MASK,
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SEL_STRB_SHIFT, STRB);
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break;
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case 50000000 ... 52000000:
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/* For both HS and DDR52 this setting works */
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
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SEL_DLY_TXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
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SEL_DLY_RXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
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ITAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
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ITAP_DLY_SEL_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
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OTAP_DLY_ENA_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
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OTAP_DLY_SEL_SHIFT, 4);
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update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
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DLL_TRIM_ICP_SHIFT, 0x8);
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update_reg(tbh_phy, PHY_CFG_0,
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DR_TY_MASK, DR_TY_SHIFT, 0x1);
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break;
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case 400000:
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
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SEL_DLY_TXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
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SEL_DLY_RXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
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ITAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
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ITAP_DLY_SEL_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
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OTAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
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OTAP_DLY_SEL_SHIFT, 0);
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update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
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DLL_TRIM_ICP_SHIFT, 0);
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update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
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break;
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default:
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
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SEL_DLY_TXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
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SEL_DLY_RXCLK_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
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ITAP_DLY_ENA_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
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ITAP_DLY_SEL_SHIFT, 0x0);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
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OTAP_DLY_ENA_SHIFT, 0x1);
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update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
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OTAP_DLY_SEL_SHIFT, 2);
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update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
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DLL_TRIM_ICP_SHIFT, 0x8);
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update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
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DR_TY_SHIFT, 0x1);
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break;
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}
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/* Reset, init seq called without phy_power_off, this indicates init seq */
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tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
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}
|
|
|
|
update_reg(tbh_phy, PHY_CFG_0, RETRIM_EN_MASK, RETRIM_EN_SHIFT, 0x1);
|
|
update_reg(tbh_phy, PHY_CFG_0, RETRIM_MASK, RETRIM_SHIFT, 0x0);
|
|
|
|
return thunderbay_emmc_phy_power(phy, 1);
|
|
}
|
|
|
|
static int thunderbay_emmc_phy_power_off(struct phy *phy)
|
|
{
|
|
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
|
|
|
|
tbh_phy->phy_power_sts = PHY_INITIALIZED;
|
|
|
|
return thunderbay_emmc_phy_power(phy, 0);
|
|
}
|
|
|
|
static const struct phy_ops thunderbay_emmc_phy_ops = {
|
|
.init = thunderbay_emmc_phy_init,
|
|
.exit = thunderbay_emmc_phy_exit,
|
|
.power_on = thunderbay_emmc_phy_power_on,
|
|
.power_off = thunderbay_emmc_phy_power_off,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static const struct of_device_id thunderbay_emmc_phy_of_match[] = {
|
|
{ .compatible = "intel,thunderbay-emmc-phy",
|
|
(void *)&thunderbay_emmc_phy_ops },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, thunderbay_emmc_phy_of_match);
|
|
|
|
static int thunderbay_emmc_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct thunderbay_emmc_phy *tbh_phy;
|
|
struct phy_provider *phy_provider;
|
|
struct device *dev = &pdev->dev;
|
|
const struct of_device_id *id;
|
|
struct phy *generic_phy;
|
|
struct resource *res;
|
|
|
|
if (!dev->of_node)
|
|
return -ENODEV;
|
|
|
|
tbh_phy = devm_kzalloc(dev, sizeof(*tbh_phy), GFP_KERNEL);
|
|
if (!tbh_phy)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
tbh_phy->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(tbh_phy->reg_base))
|
|
return PTR_ERR(tbh_phy->reg_base);
|
|
|
|
tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
|
|
id = of_match_node(thunderbay_emmc_phy_of_match, pdev->dev.of_node);
|
|
if (!id) {
|
|
dev_err(dev, "failed to get match_node\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
generic_phy = devm_phy_create(dev, dev->of_node, id->data);
|
|
if (IS_ERR(generic_phy)) {
|
|
dev_err(dev, "failed to create PHY\n");
|
|
return PTR_ERR(generic_phy);
|
|
}
|
|
|
|
phy_set_drvdata(generic_phy, tbh_phy);
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static struct platform_driver thunderbay_emmc_phy_driver = {
|
|
.probe = thunderbay_emmc_phy_probe,
|
|
.driver = {
|
|
.name = "thunderbay-emmc-phy",
|
|
.of_match_table = thunderbay_emmc_phy_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(thunderbay_emmc_phy_driver);
|
|
|
|
MODULE_AUTHOR("Nandhini S <nandhini.srikandan@intel.com>");
|
|
MODULE_AUTHOR("Rashmi A <rashmi.a@intel.com>");
|
|
MODULE_DESCRIPTION("Intel Thunder Bay eMMC PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|