267 lines
6.3 KiB
C
267 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (c) Copyright 2002-2010, Ralink Technology, Inc.
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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* Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
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*/
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#include "mt76x0.h"
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#include "eeprom.h"
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#include "mcu.h"
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#include "initvals.h"
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#include "initvals_init.h"
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#include "../mt76x02_phy.h"
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static void
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mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable)
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{
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u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD;
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/* Note: we don't turn off WLAN_CLK because that makes the device
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* not respond properly on the probe path.
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* In case anyone (PSM?) wants to use this function we can
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* bring the clock stuff back and fixup the probe path.
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*/
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if (enable)
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val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
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MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
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else
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val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
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mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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/* Note: vendor driver tries to disable/enable wlan here and retry
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* but the code which does it is so buggy it must have never
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* triggered, so don't bother.
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*/
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if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000))
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dev_err(dev->mt76.dev, "PLL and XTAL check failed\n");
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}
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void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset)
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{
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u32 val;
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val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
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if (reset) {
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val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
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val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
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if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
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val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
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MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
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mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
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MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
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}
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}
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mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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mt76x0_set_wlan_state(dev, val, enable);
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}
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EXPORT_SYMBOL_GPL(mt76x0_chip_onoff);
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static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev)
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{
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mt76_wr(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_RESET_CSR |
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MT_MAC_SYS_CTRL_RESET_BBP);
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msleep(200);
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mt76_clear(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_RESET_CSR |
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MT_MAC_SYS_CTRL_RESET_BBP);
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}
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#define RANDOM_WRITE(dev, tab) \
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mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \
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tab, ARRAY_SIZE(tab))
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static int mt76x0_init_bbp(struct mt76x02_dev *dev)
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{
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int ret, i;
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ret = mt76x0_phy_wait_bbp_ready(dev);
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if (ret)
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return ret;
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RANDOM_WRITE(dev, mt76x0_bbp_init_tab);
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for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
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const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
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const struct mt76_reg_pair *pair = &item->reg_pair;
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if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
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mt76_wr(dev, pair->reg, pair->value);
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}
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RANDOM_WRITE(dev, mt76x0_dcoc_tab);
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return 0;
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}
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static void mt76x0_init_mac_registers(struct mt76x02_dev *dev)
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{
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RANDOM_WRITE(dev, common_mac_reg_table);
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/* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
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RANDOM_WRITE(dev, mt76x0_mac_reg_table);
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/* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */
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mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3);
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/* Set 0x141C[15:12]=0xF */
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mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
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mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
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/*
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* tx_ring 9 is for mgmt frame
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* tx_ring 8 is for in-band command frame.
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* WMM_RG0_TXQMA: this register setting is for FCE to
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* define the rule of tx_ring 9
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* WMM_RG1_TXQMA: this register setting is for FCE to
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* define the rule of tx_ring 8
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*/
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mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201);
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}
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void mt76x0_mac_stop(struct mt76x02_dev *dev)
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{
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int i = 200, ok = 0;
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mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
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/* Page count on TxQ */
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while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
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(mt76_rr(dev, 0x0a30) & 0x000000ff) ||
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(mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
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msleep(10);
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if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
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dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n");
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mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
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MT_MAC_SYS_CTRL_ENABLE_TX);
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/* Page count on RxQ */
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for (i = 0; i < 200; i++) {
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if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
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!mt76_rr(dev, 0x0a30) &&
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!mt76_rr(dev, 0x0a34)) {
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if (ok++ > 5)
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break;
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continue;
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}
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msleep(1);
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}
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if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
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dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n");
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}
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EXPORT_SYMBOL_GPL(mt76x0_mac_stop);
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int mt76x0_init_hardware(struct mt76x02_dev *dev)
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{
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int ret, i, k;
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if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000))
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return -EIO;
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/* Wait for ASIC ready after FW load. */
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if (!mt76x02_wait_for_mac(&dev->mt76))
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return -ETIMEDOUT;
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mt76x0_reset_csr_bbp(dev);
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ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1);
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if (ret)
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return ret;
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mt76x0_init_mac_registers(dev);
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if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
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return -EIO;
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ret = mt76x0_init_bbp(dev);
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if (ret)
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return ret;
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dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
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for (i = 0; i < 16; i++)
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for (k = 0; k < 4; k++)
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mt76x02_mac_shared_key_setup(dev, i, k, NULL);
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for (i = 0; i < 256; i++)
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mt76x02_mac_wcid_setup(dev, i, 0, NULL);
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ret = mt76x0_eeprom_init(dev);
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if (ret)
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return ret;
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mt76x0_phy_init(dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt76x0_init_hardware);
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static void
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mt76x0_init_txpower(struct mt76x02_dev *dev,
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struct ieee80211_supported_band *sband)
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{
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struct ieee80211_channel *chan;
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struct mt76_rate_power t;
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s8 tp;
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int i;
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for (i = 0; i < sband->n_channels; i++) {
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chan = &sband->channels[i];
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mt76x0_get_tx_power_per_rate(dev, chan, &t);
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mt76x0_get_power_info(dev, chan, &tp);
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chan->orig_mpwr = (mt76x02_get_max_rate_power(&t) + tp) / 2;
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chan->max_power = min_t(int, chan->max_reg_power,
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chan->orig_mpwr);
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}
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}
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int mt76x0_register_device(struct mt76x02_dev *dev)
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{
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int ret;
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ret = mt76x02_init_device(dev);
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if (ret)
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return ret;
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mt76x02_config_mac_addr_list(dev);
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ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
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ARRAY_SIZE(mt76x02_rates));
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if (ret)
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return ret;
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if (dev->mphy.cap.has_5ghz) {
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struct ieee80211_supported_band *sband;
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sband = &dev->mphy.sband_5g.sband;
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sband->vht_cap.cap &= ~IEEE80211_VHT_CAP_RXLDPC;
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mt76x0_init_txpower(dev, sband);
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}
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if (dev->mphy.cap.has_2ghz)
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mt76x0_init_txpower(dev, &dev->mphy.sband_2g.sband);
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mt76x02_init_debugfs(dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt76x0_register_device);
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