316 lines
8.2 KiB
C
316 lines
8.2 KiB
C
// SPDX-License-Identifier: ISC
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/* Copyright (C) 2019 MediaTek Inc.
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*
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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* Roy Luo <royluo@google.com>
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* Lorenzo Bianconi <lorenzo@kernel.org>
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* Felix Fietkau <nbd@nbd.name>
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*/
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#include "mt7615.h"
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#include "../dma.h"
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#include "mac.h"
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static int
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mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
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{
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static const u8 wmm_queue_map[] = {
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[IEEE80211_AC_BK] = MT7622_TXQ_AC0,
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[IEEE80211_AC_BE] = MT7622_TXQ_AC1,
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[IEEE80211_AC_VI] = MT7622_TXQ_AC2,
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[IEEE80211_AC_VO] = MT7622_TXQ_AC3,
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};
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int ret;
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int i;
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for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
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ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
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MT7615_TX_RING_SIZE / 2,
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MT_TX_RING_BASE, 0);
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if (ret)
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return ret;
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}
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ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT,
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MT7615_TX_MGMT_RING_SIZE,
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MT_TX_RING_BASE, 0);
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if (ret)
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return ret;
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return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU,
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MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
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}
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static int
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mt7615_init_tx_queues(struct mt7615_dev *dev)
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{
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int ret;
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL,
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MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
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if (ret)
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return ret;
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if (!is_mt7615(&dev->mt76))
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return mt7622_init_tx_queues_multi(dev);
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ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE,
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MT_TX_RING_BASE, 0);
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if (ret)
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return ret;
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return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU,
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MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
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}
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static int mt7615_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt7615_dev *dev;
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dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
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if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
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napi_complete(napi);
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queue_work(dev->mt76.wq, &dev->pm.wake_work);
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return 0;
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}
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mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
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if (napi_complete(napi))
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mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
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mt76_connac_pm_unref(&dev->mphy, &dev->pm);
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return 0;
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}
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static int mt7615_poll_rx(struct napi_struct *napi, int budget)
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{
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struct mt7615_dev *dev;
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int done;
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dev = container_of(napi->dev, struct mt7615_dev, mt76.napi_dev);
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if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
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napi_complete(napi);
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queue_work(dev->mt76.wq, &dev->pm.wake_work);
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return 0;
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}
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done = mt76_dma_rx_poll(napi, budget);
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mt76_connac_pm_unref(&dev->mphy, &dev->pm);
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return done;
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}
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int mt7615_wait_pdma_busy(struct mt7615_dev *dev)
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{
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struct mt76_dev *mdev = &dev->mt76;
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if (!is_mt7663(mdev)) {
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u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;
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u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);
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if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
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dev_err(mdev->dev, "PDMA engine busy\n");
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return -EIO;
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}
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return 0;
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}
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if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
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MT_PDMA_TX_IDX_BUSY, 0, 1000)) {
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dev_err(mdev->dev, "PDMA engine tx busy\n");
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return -EIO;
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}
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if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
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MT_PSE_SRC_CNT, 0, 1000)) {
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dev_err(mdev->dev, "PSE engine busy\n");
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return -EIO;
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}
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if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
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MT_PDMA_BUSY_IDX, 0, 1000)) {
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dev_err(mdev->dev, "PDMA engine busy\n");
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return -EIO;
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}
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return 0;
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}
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static void mt7622_dma_sched_init(struct mt7615_dev *dev)
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{
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u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
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int i;
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mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
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MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
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for (i = 0; i <= 5; i++)
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mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
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mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
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mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
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}
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static void mt7663_dma_sched_init(struct mt7615_dev *dev)
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{
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int i;
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mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
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MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
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/* enable refill control group 0, 1, 2, 4, 5 */
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);
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/* enable group 0, 1, 2, 4, 5, 15 */
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);
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/* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */
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for (i = 0; i < 5; i++)
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);
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/* ALTX0 and ALTX1 QID mapping to group 5 */
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
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}
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void mt7615_dma_start(struct mt7615_dev *dev)
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{
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/* start dma engine */
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mt76_set(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_EN |
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MT_WPDMA_GLO_CFG_RX_DMA_EN |
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MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
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if (is_mt7622(&dev->mt76))
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mt7622_dma_sched_init(dev);
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if (is_mt7663(&dev->mt76)) {
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mt7663_dma_sched_init(dev);
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mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK);
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}
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}
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int mt7615_dma_init(struct mt7615_dev *dev)
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{
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int rx_ring_size = MT7615_RX_RING_SIZE;
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u32 mask;
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int ret;
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mt76_dma_attach(&dev->mt76);
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mt76_wr(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
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MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
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MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
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if (is_mt7615(&dev->mt76)) {
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mt76_set(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
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mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
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mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
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mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
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mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
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mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
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mt76_set(dev, 0x7158, BIT(16));
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mt76_clear(dev, 0x7000, BIT(23));
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}
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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ret = mt7615_init_tx_queues(dev);
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if (ret)
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return ret;
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/* init rx queues */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
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MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,
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MT_RX_RING_BASE);
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if (ret)
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return ret;
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if (!is_mt7615(&dev->mt76))
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rx_ring_size /= 2;
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
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rx_ring_size, MT_RX_BUF_SIZE, MT_RX_RING_BASE);
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if (ret)
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return ret;
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mt76_wr(dev, MT_DELAY_INT_CFG, 0);
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ret = mt76_init_queues(dev, mt7615_poll_rx);
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if (ret < 0)
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return ret;
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netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
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mt7615_poll_tx);
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napi_enable(&dev->mt76.tx_napi);
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mt76_poll(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
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/* enable interrupts for TX/RX rings */
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mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev);
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if (is_mt7663(&dev->mt76))
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mask |= MT7663_INT_MCU_CMD;
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else
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mask |= MT_INT_MCU_CMD;
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mt7615_irq_enable(dev, mask);
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mt7615_dma_start(dev);
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return 0;
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}
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void mt7615_dma_cleanup(struct mt7615_dev *dev)
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{
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mt76_clear(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_EN |
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MT_WPDMA_GLO_CFG_RX_DMA_EN);
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mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
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mt76_dma_cleanup(&dev->mt76);
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}
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