382 lines
13 KiB
C
382 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
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/*
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* Copyright 2008 - 2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*/
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#ifndef __FM_H
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#define __FM_H
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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/* FM Frame descriptor macros */
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/* Frame queue Context Override */
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#define FM_FD_CMD_FCO 0x80000000
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#define FM_FD_CMD_RPD 0x40000000 /* Read Prepended Data */
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#define FM_FD_CMD_UPD 0x20000000 /* Update Prepended Data */
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#define FM_FD_CMD_DTC 0x10000000 /* Do L4 Checksum */
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/* TX-Port: Unsupported Format */
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#define FM_FD_ERR_UNSUPPORTED_FORMAT 0x04000000
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/* TX Port: Length Error */
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#define FM_FD_ERR_LENGTH 0x02000000
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#define FM_FD_ERR_DMA 0x01000000 /* DMA Data error */
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/* IPR frame (not error) */
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#define FM_FD_IPR 0x00000001
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/* IPR non-consistent-sp */
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#define FM_FD_ERR_IPR_NCSP (0x00100000 | FM_FD_IPR)
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/* IPR error */
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#define FM_FD_ERR_IPR (0x00200000 | FM_FD_IPR)
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/* IPR timeout */
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#define FM_FD_ERR_IPR_TO (0x00300000 | FM_FD_IPR)
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/* TX Port: Length Error */
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#define FM_FD_ERR_IPRE (FM_FD_ERR_IPR & ~FM_FD_IPR)
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/* Rx FIFO overflow, FCS error, code error, running disparity error
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* (SGMII and TBI modes), FIFO parity error. PHY Sequence error,
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* PHY error control character detected.
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*/
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#define FM_FD_ERR_PHYSICAL 0x00080000
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/* Frame too long OR Frame size exceeds max_length_frame */
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#define FM_FD_ERR_SIZE 0x00040000
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/* classification discard */
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#define FM_FD_ERR_CLS_DISCARD 0x00020000
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/* Extract Out of Frame */
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#define FM_FD_ERR_EXTRACTION 0x00008000
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/* No Scheme Selected */
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#define FM_FD_ERR_NO_SCHEME 0x00004000
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/* Keysize Overflow */
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#define FM_FD_ERR_KEYSIZE_OVERFLOW 0x00002000
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/* Frame color is red */
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#define FM_FD_ERR_COLOR_RED 0x00000800
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/* Frame color is yellow */
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#define FM_FD_ERR_COLOR_YELLOW 0x00000400
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/* Parser Time out Exceed */
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#define FM_FD_ERR_PRS_TIMEOUT 0x00000080
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/* Invalid Soft Parser instruction */
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#define FM_FD_ERR_PRS_ILL_INSTRUCT 0x00000040
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/* Header error was identified during parsing */
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#define FM_FD_ERR_PRS_HDR_ERR 0x00000020
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/* Frame parsed beyind 256 first bytes */
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#define FM_FD_ERR_BLOCK_LIMIT_EXCEEDED 0x00000008
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/* non Frame-Manager error */
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#define FM_FD_RX_STATUS_ERR_NON_FM 0x00400000
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/* FMan driver defines */
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#define FMAN_BMI_FIFO_UNITS 0x100
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#define OFFSET_UNITS 16
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/* BMan defines */
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#define BM_MAX_NUM_OF_POOLS 64 /* Buffers pools */
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#define FMAN_PORT_MAX_EXT_POOLS_NUM 8 /* External BM pools per Rx port */
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struct fman; /* FMan data */
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/* Enum for defining port types */
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enum fman_port_type {
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FMAN_PORT_TYPE_TX = 0, /* TX Port */
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FMAN_PORT_TYPE_RX, /* RX Port */
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};
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struct fman_rev_info {
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u8 major; /* Major revision */
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u8 minor; /* Minor revision */
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};
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enum fman_exceptions {
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FMAN_EX_DMA_BUS_ERROR = 0, /* DMA bus error. */
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FMAN_EX_DMA_READ_ECC, /* Read Buffer ECC error */
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FMAN_EX_DMA_SYSTEM_WRITE_ECC, /* Write Buffer ECC err on sys side */
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FMAN_EX_DMA_FM_WRITE_ECC, /* Write Buffer ECC error on FM side */
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FMAN_EX_DMA_SINGLE_PORT_ECC, /* Single Port ECC error on FM side */
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FMAN_EX_FPM_STALL_ON_TASKS, /* Stall of tasks on FPM */
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FMAN_EX_FPM_SINGLE_ECC, /* Single ECC on FPM. */
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FMAN_EX_FPM_DOUBLE_ECC, /* Double ECC error on FPM ram access */
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FMAN_EX_QMI_SINGLE_ECC, /* Single ECC on QMI. */
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FMAN_EX_QMI_DOUBLE_ECC, /* Double bit ECC occurred on QMI */
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FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/* DeQ from unknown port id */
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FMAN_EX_BMI_LIST_RAM_ECC, /* Linked List RAM ECC error */
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FMAN_EX_BMI_STORAGE_PROFILE_ECC,/* storage profile */
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FMAN_EX_BMI_STATISTICS_RAM_ECC,/* Statistics RAM ECC Err Enable */
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FMAN_EX_BMI_DISPATCH_RAM_ECC, /* Dispatch RAM ECC Error Enable */
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FMAN_EX_IRAM_ECC, /* Double bit ECC occurred on IRAM */
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FMAN_EX_MURAM_ECC /* Double bit ECC occurred on MURAM */
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};
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/* Parse results memory layout */
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struct fman_prs_result {
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u8 lpid; /* Logical port id */
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u8 shimr; /* Shim header result */
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__be16 l2r; /* Layer 2 result */
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__be16 l3r; /* Layer 3 result */
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u8 l4r; /* Layer 4 result */
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u8 cplan; /* Classification plan id */
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__be16 nxthdr; /* Next Header */
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__be16 cksum; /* Running-sum */
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/* Flags&fragment-offset field of the last IP-header */
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__be16 flags_frag_off;
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/* Routing type field of a IPV6 routing extension header */
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u8 route_type;
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/* Routing Extension Header Present; last bit is IP valid */
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u8 rhp_ip_valid;
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u8 shim_off[2]; /* Shim offset */
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u8 ip_pid_off; /* IP PID (last IP-proto) offset */
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u8 eth_off; /* ETH offset */
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u8 llc_snap_off; /* LLC_SNAP offset */
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u8 vlan_off[2]; /* VLAN offset */
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u8 etype_off; /* ETYPE offset */
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u8 pppoe_off; /* PPP offset */
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u8 mpls_off[2]; /* MPLS offset */
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u8 ip_off[2]; /* IP offset */
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u8 gre_off; /* GRE offset */
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u8 l4_off; /* Layer 4 offset */
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u8 nxthdr_off; /* Parser end point */
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};
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/* A structure for defining buffer prefix area content. */
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struct fman_buffer_prefix_content {
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/* Number of bytes to be left at the beginning of the external
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* buffer; Note that the private-area will start from the base
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* of the buffer address.
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*/
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u16 priv_data_size;
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/* true to pass the parse result to/from the FM;
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* User may use FM_PORT_GetBufferPrsResult() in
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* order to get the parser-result from a buffer.
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*/
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bool pass_prs_result;
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/* true to pass the timeStamp to/from the FM User */
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bool pass_time_stamp;
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/* true to pass the KG hash result to/from the FM User may
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* use FM_PORT_GetBufferHashResult() in order to get the
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* parser-result from a buffer.
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*/
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bool pass_hash_result;
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/* Add all other Internal-Context information: AD,
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* hash-result, key, etc.
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*/
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u16 data_align;
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};
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/* A structure of information about each of the external
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* buffer pools used by a port or storage-profile.
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*/
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struct fman_ext_pool_params {
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u8 id; /* External buffer pool id */
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u16 size; /* External buffer pool buffer size */
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};
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/* A structure for informing the driver about the external
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* buffer pools allocated in the BM and used by a port or a
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* storage-profile.
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*/
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struct fman_ext_pools {
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u8 num_of_pools_used; /* Number of pools use by this port */
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struct fman_ext_pool_params ext_buf_pool[FMAN_PORT_MAX_EXT_POOLS_NUM];
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/* Parameters for each port */
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};
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/* A structure for defining BM pool depletion criteria */
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struct fman_buf_pool_depletion {
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/* select mode in which pause frames will be sent after a
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* number of pools (all together!) are depleted
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*/
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bool pools_grp_mode_enable;
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/* the number of depleted pools that will invoke pause
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* frames transmission.
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*/
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u8 num_of_pools;
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/* For each pool, true if it should be considered for
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* depletion (Note - this pool must be used by this port!).
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*/
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bool pools_to_consider[BM_MAX_NUM_OF_POOLS];
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/* select mode in which pause frames will be sent
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* after a single-pool is depleted;
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*/
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bool single_pool_mode_enable;
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/* For each pool, true if it should be considered
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* for depletion (Note - this pool must be used by this port!)
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*/
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bool pools_to_consider_for_single_mode[BM_MAX_NUM_OF_POOLS];
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};
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/* Enum for inter-module interrupts registration */
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enum fman_event_modules {
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FMAN_MOD_MAC = 0, /* MAC event */
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FMAN_MOD_FMAN_CTRL, /* FMAN Controller */
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FMAN_MOD_DUMMY_LAST
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};
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/* Enum for interrupts types */
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enum fman_intr_type {
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FMAN_INTR_TYPE_ERR,
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FMAN_INTR_TYPE_NORMAL
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};
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/* Enum for inter-module interrupts registration */
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enum fman_inter_module_event {
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FMAN_EV_ERR_MAC0 = 0, /* MAC 0 error event */
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FMAN_EV_ERR_MAC1, /* MAC 1 error event */
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FMAN_EV_ERR_MAC2, /* MAC 2 error event */
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FMAN_EV_ERR_MAC3, /* MAC 3 error event */
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FMAN_EV_ERR_MAC4, /* MAC 4 error event */
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FMAN_EV_ERR_MAC5, /* MAC 5 error event */
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FMAN_EV_ERR_MAC6, /* MAC 6 error event */
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FMAN_EV_ERR_MAC7, /* MAC 7 error event */
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FMAN_EV_ERR_MAC8, /* MAC 8 error event */
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FMAN_EV_ERR_MAC9, /* MAC 9 error event */
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FMAN_EV_MAC0, /* MAC 0 event (Magic packet detection) */
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FMAN_EV_MAC1, /* MAC 1 event (Magic packet detection) */
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FMAN_EV_MAC2, /* MAC 2 (Magic packet detection) */
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FMAN_EV_MAC3, /* MAC 3 (Magic packet detection) */
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FMAN_EV_MAC4, /* MAC 4 (Magic packet detection) */
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FMAN_EV_MAC5, /* MAC 5 (Magic packet detection) */
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FMAN_EV_MAC6, /* MAC 6 (Magic packet detection) */
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FMAN_EV_MAC7, /* MAC 7 (Magic packet detection) */
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FMAN_EV_MAC8, /* MAC 8 event (Magic packet detection) */
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FMAN_EV_MAC9, /* MAC 9 event (Magic packet detection) */
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FMAN_EV_FMAN_CTRL_0, /* Fman controller event 0 */
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FMAN_EV_FMAN_CTRL_1, /* Fman controller event 1 */
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FMAN_EV_FMAN_CTRL_2, /* Fman controller event 2 */
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FMAN_EV_FMAN_CTRL_3, /* Fman controller event 3 */
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FMAN_EV_CNT
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};
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struct fman_intr_src {
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void (*isr_cb)(void *src_arg);
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void *src_handle;
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};
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/** fman_exceptions_cb
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* fman - Pointer to FMan
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* exception - The exception.
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*
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* Exceptions user callback routine, will be called upon an exception
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* passing the exception identification.
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*
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* Return: irq status
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*/
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typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman,
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enum fman_exceptions exception);
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/** fman_bus_error_cb
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* fman - Pointer to FMan
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* port_id - Port id
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* addr - Address that caused the error
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* tnum - Owner of error
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* liodn - Logical IO device number
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*
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* Bus error user callback routine, will be called upon bus error,
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* passing parameters describing the errors and the owner.
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*
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* Return: IRQ status
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*/
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typedef irqreturn_t (fman_bus_error_cb)(struct fman *fman, u8 port_id,
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u64 addr, u8 tnum, u16 liodn);
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/* Structure that holds information received from device tree */
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struct fman_dts_params {
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void __iomem *base_addr; /* FMan virtual address */
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struct resource *res; /* FMan memory resource */
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u8 id; /* FMan ID */
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int err_irq; /* FMan Error IRQ */
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u16 clk_freq; /* FMan clock freq (In Mhz) */
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u32 qman_channel_base; /* QMan channels base */
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u32 num_of_qman_channels; /* Number of QMan channels */
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struct resource muram_res; /* MURAM resource */
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};
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struct fman {
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struct device *dev;
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void __iomem *base_addr;
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struct fman_intr_src intr_mng[FMAN_EV_CNT];
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struct fman_fpm_regs __iomem *fpm_regs;
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struct fman_bmi_regs __iomem *bmi_regs;
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struct fman_qmi_regs __iomem *qmi_regs;
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struct fman_dma_regs __iomem *dma_regs;
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struct fman_hwp_regs __iomem *hwp_regs;
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struct fman_kg_regs __iomem *kg_regs;
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fman_exceptions_cb *exception_cb;
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fman_bus_error_cb *bus_error_cb;
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/* Spinlock for FMan use */
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spinlock_t spinlock;
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struct fman_state_struct *state;
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struct fman_cfg *cfg;
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struct muram_info *muram;
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struct fman_keygen *keygen;
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/* cam section in muram */
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unsigned long cam_offset;
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size_t cam_size;
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/* Fifo in MURAM */
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unsigned long fifo_offset;
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size_t fifo_size;
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u32 liodn_base[64];
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u32 liodn_offset[64];
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struct fman_dts_params dts_params;
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};
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/* Structure for port-FM communication during fman_port_init. */
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struct fman_port_init_params {
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u8 port_id; /* port Id */
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enum fman_port_type port_type; /* Port type */
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u16 port_speed; /* Port speed */
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u16 liodn_offset; /* Port's requested resource */
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u8 num_of_tasks; /* Port's requested resource */
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u8 num_of_extra_tasks; /* Port's requested resource */
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u8 num_of_open_dmas; /* Port's requested resource */
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u8 num_of_extra_open_dmas; /* Port's requested resource */
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u32 size_of_fifo; /* Port's requested resource */
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u32 extra_size_of_fifo; /* Port's requested resource */
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u8 deq_pipeline_depth; /* Port's requested resource */
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u16 max_frame_length; /* Port's max frame length. */
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u16 liodn_base;
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/* LIODN base for this port, to be used together with LIODN offset. */
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};
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void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info);
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void fman_register_intr(struct fman *fman, enum fman_event_modules mod,
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u8 mod_id, enum fman_intr_type intr_type,
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void (*f_isr)(void *h_src_arg), void *h_src_arg);
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void fman_unregister_intr(struct fman *fman, enum fman_event_modules mod,
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u8 mod_id, enum fman_intr_type intr_type);
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int fman_set_port_params(struct fman *fman,
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struct fman_port_init_params *port_params);
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int fman_reset_mac(struct fman *fman, u8 mac_id);
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u16 fman_get_clock_freq(struct fman *fman);
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u32 fman_get_bmi_max_fifo_size(struct fman *fman);
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int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl);
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u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id);
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struct resource *fman_get_mem_region(struct fman *fman);
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u16 fman_get_max_frm(void);
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int fman_get_rx_extra_headroom(void);
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#ifdef CONFIG_DPAA_ERRATUM_A050385
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bool fman_has_errata_a050385(void);
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#endif
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struct fman *fman_bind(struct device *dev);
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#endif /* __FM_H */
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