768 lines
22 KiB
C
768 lines
22 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Kevin Tian <kevin.tian@intel.com>
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* Eddie Dong <eddie.dong@intel.com>
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*
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* Contributors:
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* Niu Bing <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_H_
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#define _GVT_H_
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#include <uapi/linux/pci_regs.h>
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#include <linux/kvm_host.h>
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#include <linux/vfio.h>
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#include <linux/mdev.h>
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#include "i915_drv.h"
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#include "intel_gvt.h"
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#include "debug.h"
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#include "mmio.h"
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#include "reg.h"
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#include "interrupt.h"
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#include "gtt.h"
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#include "display.h"
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#include "edid.h"
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#include "execlist.h"
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#include "scheduler.h"
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#include "sched_policy.h"
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#include "mmio_context.h"
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#include "cmd_parser.h"
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#include "fb_decoder.h"
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#include "dmabuf.h"
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#include "page_track.h"
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#define GVT_MAX_VGPU 8
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/* Describe per-platform limitations. */
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struct intel_gvt_device_info {
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u32 max_support_vgpus;
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u32 cfg_space_size;
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u32 mmio_size;
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u32 mmio_bar;
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unsigned long msi_cap_offset;
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u32 gtt_start_offset;
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u32 gtt_entry_size;
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u32 gtt_entry_size_shift;
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int gmadr_bytes_in_cmd;
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u32 max_surface_size;
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};
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/* GM resources owned by a vGPU */
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struct intel_vgpu_gm {
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u64 aperture_sz;
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u64 hidden_sz;
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struct drm_mm_node low_gm_node;
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struct drm_mm_node high_gm_node;
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};
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#define INTEL_GVT_MAX_NUM_FENCES 32
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/* Fences owned by a vGPU */
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struct intel_vgpu_fence {
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struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
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u32 base;
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u32 size;
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};
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struct intel_vgpu_mmio {
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void *vreg;
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};
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#define INTEL_GVT_MAX_BAR_NUM 4
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struct intel_vgpu_pci_bar {
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u64 size;
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bool tracked;
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};
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struct intel_vgpu_cfg_space {
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unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
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struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
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u32 pmcsr_off;
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};
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#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
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struct intel_vgpu_irq {
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bool irq_warn_once[INTEL_GVT_EVENT_MAX];
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DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
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INTEL_GVT_EVENT_MAX);
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};
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struct intel_vgpu_opregion {
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bool mapped;
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void *va;
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u32 gfn[INTEL_GVT_OPREGION_PAGES];
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};
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#define vgpu_opregion(vgpu) (&(vgpu->opregion))
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struct intel_vgpu_display {
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struct intel_vgpu_i2c_edid i2c_edid;
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struct intel_vgpu_port ports[I915_MAX_PORTS];
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struct intel_vgpu_sbi sbi;
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enum port port_num;
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};
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struct vgpu_sched_ctl {
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int weight;
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};
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enum {
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INTEL_VGPU_EXECLIST_SUBMISSION = 1,
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INTEL_VGPU_GUC_SUBMISSION,
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};
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struct intel_vgpu_submission_ops {
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const char *name;
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int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
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void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
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void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
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};
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struct intel_vgpu_submission {
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struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
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struct list_head workload_q_head[I915_NUM_ENGINES];
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struct intel_context *shadow[I915_NUM_ENGINES];
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struct kmem_cache *workloads;
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atomic_t running_workload_num;
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union {
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u64 i915_context_pml4;
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u64 i915_context_pdps[GEN8_3LVL_PDPES];
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};
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DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
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DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
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void *ring_scan_buffer[I915_NUM_ENGINES];
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int ring_scan_buffer_size[I915_NUM_ENGINES];
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const struct intel_vgpu_submission_ops *ops;
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int virtual_submission_interface;
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bool active;
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struct {
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u32 lrca;
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bool valid;
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u64 ring_context_gpa;
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} last_ctx[I915_NUM_ENGINES];
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};
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#define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries"
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struct intel_vgpu {
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struct vfio_device vfio_device;
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struct intel_gvt *gvt;
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struct mutex vgpu_lock;
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int id;
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bool active;
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bool attached;
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bool pv_notified;
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bool failsafe;
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unsigned int resetting_eng;
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/* Both sched_data and sched_ctl can be seen a part of the global gvt
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* scheduler structure. So below 2 vgpu data are protected
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* by sched_lock, not vgpu_lock.
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*/
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void *sched_data;
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struct vgpu_sched_ctl sched_ctl;
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struct intel_vgpu_fence fence;
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struct intel_vgpu_gm gm;
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struct intel_vgpu_cfg_space cfg_space;
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struct intel_vgpu_mmio mmio;
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struct intel_vgpu_irq irq;
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struct intel_vgpu_gtt gtt;
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struct intel_vgpu_opregion opregion;
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struct intel_vgpu_display display;
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struct intel_vgpu_submission submission;
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struct radix_tree_root page_track_tree;
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u32 hws_pga[I915_NUM_ENGINES];
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/* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
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bool d3_entered;
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struct dentry *debugfs;
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struct list_head dmabuf_obj_list_head;
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struct mutex dmabuf_lock;
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struct idr object_idr;
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struct intel_vgpu_vblank_timer vblank_timer;
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u32 scan_nonprivbb;
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struct vfio_region *region;
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int num_regions;
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struct eventfd_ctx *intx_trigger;
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struct eventfd_ctx *msi_trigger;
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/*
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* Two caches are used to avoid mapping duplicated pages (eg.
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* scratch pages). This help to reduce dma setup overhead.
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*/
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struct rb_root gfn_cache;
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struct rb_root dma_addr_cache;
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unsigned long nr_cache_entries;
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struct mutex cache_lock;
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atomic_t released;
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struct kvm_page_track_notifier_node track_node;
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#define NR_BKT (1 << 18)
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struct hlist_head ptable[NR_BKT];
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#undef NR_BKT
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};
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/* validating GM healthy status*/
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#define vgpu_is_vm_unhealthy(ret_val) \
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(((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
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struct intel_gvt_gm {
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unsigned long vgpu_allocated_low_gm_size;
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unsigned long vgpu_allocated_high_gm_size;
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};
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struct intel_gvt_fence {
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unsigned long vgpu_allocated_fence_num;
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};
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/* Special MMIO blocks. */
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struct gvt_mmio_block {
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unsigned int device;
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i915_reg_t offset;
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unsigned int size;
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gvt_mmio_func read;
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gvt_mmio_func write;
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};
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#define INTEL_GVT_MMIO_HASH_BITS 11
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struct intel_gvt_mmio {
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u16 *mmio_attribute;
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/* Register contains RO bits */
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#define F_RO (1 << 0)
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/* Register contains graphics address */
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#define F_GMADR (1 << 1)
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/* Mode mask registers with high 16 bits as the mask bits */
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#define F_MODE_MASK (1 << 2)
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/* This reg can be accessed by GPU commands */
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#define F_CMD_ACCESS (1 << 3)
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/* This reg has been accessed by a VM */
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#define F_ACCESSED (1 << 4)
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/* This reg requires save & restore during host PM suspend/resume */
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#define F_PM_SAVE (1 << 5)
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/* This reg could be accessed by unaligned address */
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#define F_UNALIGN (1 << 6)
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/* This reg is in GVT's mmio save-restor list and in hardware
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* logical context image
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*/
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#define F_SR_IN_CTX (1 << 7)
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/* Value of command write of this reg needs to be patched */
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#define F_CMD_WRITE_PATCH (1 << 8)
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struct gvt_mmio_block *mmio_block;
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unsigned int num_mmio_block;
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DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
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unsigned long num_tracked_mmio;
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};
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struct intel_gvt_firmware {
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void *cfg_space;
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void *mmio;
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bool firmware_loaded;
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};
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struct intel_vgpu_config {
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unsigned int low_mm;
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unsigned int high_mm;
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unsigned int fence;
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/*
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* A vGPU with a weight of 8 will get twice as much GPU as a vGPU with
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* a weight of 4 on a contended host, different vGPU type has different
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* weight set. Legal weights range from 1 to 16.
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*/
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unsigned int weight;
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enum intel_vgpu_edid edid;
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const char *name;
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};
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struct intel_vgpu_type {
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struct mdev_type type;
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char name[16];
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const struct intel_vgpu_config *conf;
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};
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struct intel_gvt {
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/* GVT scope lock, protect GVT itself, and all resource currently
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* not yet protected by special locks(vgpu and scheduler lock).
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*/
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struct mutex lock;
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/* scheduler scope lock, protect gvt and vgpu schedule related data */
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struct mutex sched_lock;
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struct intel_gt *gt;
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struct idr vgpu_idr; /* vGPU IDR pool */
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struct intel_gvt_device_info device_info;
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struct intel_gvt_gm gm;
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struct intel_gvt_fence fence;
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struct intel_gvt_mmio mmio;
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struct intel_gvt_firmware firmware;
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struct intel_gvt_irq irq;
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struct intel_gvt_gtt gtt;
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struct intel_gvt_workload_scheduler scheduler;
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struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
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DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
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struct mdev_parent parent;
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struct mdev_type **mdev_types;
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struct intel_vgpu_type *types;
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unsigned int num_types;
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struct intel_vgpu *idle_vgpu;
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struct task_struct *service_thread;
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wait_queue_head_t service_thread_wq;
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/* service_request is always used in bit operation, we should always
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* use it with atomic bit ops so that no need to use gvt big lock.
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*/
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unsigned long service_request;
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struct {
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struct engine_mmio *mmio;
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int ctx_mmio_count[I915_NUM_ENGINES];
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u32 *tlb_mmio_offset_list;
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u32 tlb_mmio_offset_list_cnt;
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u32 *mocs_mmio_offset_list;
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u32 mocs_mmio_offset_list_cnt;
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} engine_mmio_list;
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bool is_reg_whitelist_updated;
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struct dentry *debugfs_root;
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};
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static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
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{
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return i915->gvt;
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}
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enum {
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/* Scheduling trigger by timer */
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INTEL_GVT_REQUEST_SCHED = 0,
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/* Scheduling trigger by event */
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INTEL_GVT_REQUEST_EVENT_SCHED = 1,
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/* per-vGPU vblank emulation request */
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INTEL_GVT_REQUEST_EMULATE_VBLANK = 2,
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INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK
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+ GVT_MAX_VGPU,
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};
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static inline void intel_gvt_request_service(struct intel_gvt *gvt,
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int service)
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{
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set_bit(service, (void *)&gvt->service_request);
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wake_up(&gvt->service_thread_wq);
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}
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void intel_gvt_free_firmware(struct intel_gvt *gvt);
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int intel_gvt_load_firmware(struct intel_gvt *gvt);
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/* Aperture/GM space definitions for GVT device */
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#define MB_TO_BYTES(mb) ((mb) << 20ULL)
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#define BYTES_TO_MB(b) ((b) >> 20ULL)
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#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
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#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
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#define HOST_FENCE 4
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#define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
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/* Aperture/GM space definitions for GVT device */
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#define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
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#define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
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#define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
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#define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
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#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
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#define gvt_aperture_gmadr_base(gvt) (0)
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#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
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+ gvt_aperture_sz(gvt) - 1)
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#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
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+ gvt_aperture_sz(gvt))
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#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
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+ gvt_hidden_sz(gvt) - 1)
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#define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
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/* Aperture/GM space definitions for vGPU */
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#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
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#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
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#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
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#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
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#define vgpu_aperture_pa_base(vgpu) \
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(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
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#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
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#define vgpu_aperture_pa_end(vgpu) \
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(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
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#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
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#define vgpu_aperture_gmadr_end(vgpu) \
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(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
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#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
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#define vgpu_hidden_gmadr_end(vgpu) \
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(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
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#define vgpu_fence_base(vgpu) (vgpu->fence.base)
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#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
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/* ring context size i.e. the first 0x50 dwords*/
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#define RING_CTX_SIZE 320
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int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
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const struct intel_vgpu_config *conf);
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void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
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void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
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void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
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u32 fence, u64 value);
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/* Macros for easily accessing vGPU virtual/shadow register.
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Explicitly seperate use for typed MMIO reg or real offset.*/
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#define vgpu_vreg_t(vgpu, reg) \
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(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
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#define vgpu_vreg(vgpu, offset) \
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(*(u32 *)(vgpu->mmio.vreg + (offset)))
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#define vgpu_vreg64_t(vgpu, reg) \
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(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
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#define vgpu_vreg64(vgpu, offset) \
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(*(u64 *)(vgpu->mmio.vreg + (offset)))
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#define for_each_active_vgpu(gvt, vgpu, id) \
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idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
|
|
for_each_if(vgpu->active)
|
|
|
|
static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
|
|
u32 offset, u32 val, bool low)
|
|
{
|
|
u32 *pval;
|
|
|
|
/* BAR offset should be 32 bits algiend */
|
|
offset = rounddown(offset, 4);
|
|
pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
|
|
|
|
if (low) {
|
|
/*
|
|
* only update bit 31 - bit 4,
|
|
* leave the bit 3 - bit 0 unchanged.
|
|
*/
|
|
*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
|
|
} else {
|
|
*pval = val;
|
|
}
|
|
}
|
|
|
|
int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
|
|
void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
|
|
|
|
struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
|
|
void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
|
|
int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
|
|
const struct intel_vgpu_config *conf);
|
|
void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
|
|
void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
|
|
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
|
|
intel_engine_mask_t engine_mask);
|
|
void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
|
|
void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
|
|
void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
|
|
|
|
int intel_gvt_set_opregion(struct intel_vgpu *vgpu);
|
|
int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num);
|
|
|
|
/* validating GM functions */
|
|
#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
|
|
((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
|
|
(gmadr <= vgpu_aperture_gmadr_end(vgpu)))
|
|
|
|
#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
|
|
((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
|
|
(gmadr <= vgpu_hidden_gmadr_end(vgpu)))
|
|
|
|
#define vgpu_gmadr_is_valid(vgpu, gmadr) \
|
|
((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
|
|
(vgpu_gmadr_is_hidden(vgpu, gmadr))))
|
|
|
|
#define gvt_gmadr_is_aperture(gvt, gmadr) \
|
|
((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
|
|
(gmadr <= gvt_aperture_gmadr_end(gvt)))
|
|
|
|
#define gvt_gmadr_is_hidden(gvt, gmadr) \
|
|
((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
|
|
(gmadr <= gvt_hidden_gmadr_end(gvt)))
|
|
|
|
#define gvt_gmadr_is_valid(gvt, gmadr) \
|
|
(gvt_gmadr_is_aperture(gvt, gmadr) || \
|
|
gvt_gmadr_is_hidden(gvt, gmadr))
|
|
|
|
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
|
|
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
|
|
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
|
|
int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
|
|
unsigned long *h_index);
|
|
int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
|
|
unsigned long *g_index);
|
|
|
|
void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
|
|
bool primary);
|
|
void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
|
|
|
|
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
|
|
void *p_data, unsigned int bytes);
|
|
|
|
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
|
|
void *p_data, unsigned int bytes);
|
|
|
|
void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
|
|
|
|
static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
|
|
{
|
|
/* We are 64bit bar. */
|
|
return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
|
|
PCI_BASE_ADDRESS_MEM_MASK;
|
|
}
|
|
|
|
void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
|
|
int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
|
|
int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
|
|
|
|
int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
|
|
void populate_pvinfo_page(struct intel_vgpu *vgpu);
|
|
|
|
int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
|
|
void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
|
|
void intel_vgpu_detach_regions(struct intel_vgpu *vgpu);
|
|
|
|
enum {
|
|
GVT_FAILSAFE_UNSUPPORTED_GUEST,
|
|
GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
|
|
GVT_FAILSAFE_GUEST_ERR,
|
|
};
|
|
|
|
static inline void mmio_hw_access_pre(struct intel_gt *gt)
|
|
{
|
|
intel_runtime_pm_get(gt->uncore->rpm);
|
|
}
|
|
|
|
static inline void mmio_hw_access_post(struct intel_gt *gt)
|
|
{
|
|
intel_runtime_pm_put_unchecked(gt->uncore->rpm);
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
*/
|
|
static inline void intel_gvt_mmio_set_accessed(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
* Returns:
|
|
* True if an MMIO is able to be accessed by GPU commands
|
|
*/
|
|
static inline bool intel_gvt_mmio_is_cmd_accessible(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_set_cmd_accessible -
|
|
* mark a MMIO could be accessible by command
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
*/
|
|
static inline void intel_gvt_mmio_set_cmd_accessible(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
*/
|
|
static inline bool intel_gvt_mmio_is_unalign(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
* Returns:
|
|
* True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
|
|
*
|
|
*/
|
|
static inline bool intel_gvt_mmio_has_mode_mask(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_is_sr_in_ctx -
|
|
* check if an MMIO has F_SR_IN_CTX mask
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
* Returns:
|
|
* True if an MMIO has an F_SR_IN_CTX mask, false if it isn't.
|
|
*
|
|
*/
|
|
static inline bool intel_gvt_mmio_is_sr_in_ctx(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_set_sr_in_ctx -
|
|
* mask an MMIO in GVT's mmio save-restore list and also
|
|
* in hardware logical context image
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
*/
|
|
static inline void intel_gvt_mmio_set_sr_in_ctx(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
|
|
}
|
|
|
|
void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
|
|
/**
|
|
* intel_gvt_mmio_set_cmd_write_patch -
|
|
* mark an MMIO if its cmd write needs to be
|
|
* patched
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
*/
|
|
static inline void intel_gvt_mmio_set_cmd_write_patch(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to
|
|
* be patched
|
|
* @gvt: a GVT device
|
|
* @offset: register offset
|
|
*
|
|
* Returns:
|
|
* True if GPU commmand write to an MMIO should be patched
|
|
*/
|
|
static inline bool intel_gvt_mmio_is_cmd_write_patch(
|
|
struct intel_gvt *gvt, unsigned int offset)
|
|
{
|
|
return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH;
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_read_gpa - copy data from GPA to host data buffer
|
|
* @vgpu: a vGPU
|
|
* @gpa: guest physical address
|
|
* @buf: host data buffer
|
|
* @len: data length
|
|
*
|
|
* Returns:
|
|
* Zero on success, negative error code if failed.
|
|
*/
|
|
static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa,
|
|
void *buf, unsigned long len)
|
|
{
|
|
if (!vgpu->attached)
|
|
return -ESRCH;
|
|
return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);
|
|
}
|
|
|
|
/**
|
|
* intel_gvt_write_gpa - copy data from host data buffer to GPA
|
|
* @vgpu: a vGPU
|
|
* @gpa: guest physical address
|
|
* @buf: host data buffer
|
|
* @len: data length
|
|
*
|
|
* Returns:
|
|
* Zero on success, negative error code if failed.
|
|
*/
|
|
static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu,
|
|
unsigned long gpa, void *buf, unsigned long len)
|
|
{
|
|
if (!vgpu->attached)
|
|
return -ESRCH;
|
|
return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);
|
|
}
|
|
|
|
void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
|
|
void intel_gvt_debugfs_init(struct intel_gvt *gvt);
|
|
void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
|
|
|
|
int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn);
|
|
int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn);
|
|
int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr);
|
|
int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
|
|
unsigned long size, dma_addr_t *dma_addr);
|
|
void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu,
|
|
dma_addr_t dma_addr);
|
|
|
|
#include "trace.h"
|
|
|
|
#endif
|