523 lines
16 KiB
C
523 lines
16 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt_mcr.h"
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#include "intel_gt_regs.h"
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/**
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* DOC: GT Multicast/Replicated (MCR) Register Support
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*
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* Some GT registers are designed as "multicast" or "replicated" registers:
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* multiple instances of the same register share a single MMIO offset. MCR
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* registers are generally used when the hardware needs to potentially track
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* independent values of a register per hardware unit (e.g., per-subslice,
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* per-L3bank, etc.). The specific types of replication that exist vary
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* per-platform.
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*
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* MMIO accesses to MCR registers are controlled according to the settings
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* programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR
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* registers can be done in either a (i.e., a single write updates all
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* instances of the register to the same value) or unicast (a write updates only
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* one specific instance). Reads of MCR registers always operate in a unicast
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* manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR.
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* Selection of a specific MCR instance for unicast operations is referred to
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* as "steering."
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*
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* If MCR register operations are steered toward a hardware unit that is
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* fused off or currently powered down due to power gating, the MMIO operation
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* is "terminated" by the hardware. Terminated read operations will return a
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* value of zero and terminated unicast write operations will be silently
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* ignored.
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*/
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#define HAS_MSLICE_STEERING(dev_priv) (INTEL_INFO(dev_priv)->has_mslice_steering)
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static const char * const intel_steering_types[] = {
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"L3BANK",
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"MSLICE",
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"LNCF",
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"INSTANCE 0",
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};
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static const struct intel_mmio_range icl_l3bank_steering_table[] = {
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{ 0x00B100, 0x00B3FF },
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{},
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};
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static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
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{ 0x004000, 0x004AFF },
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{ 0x00C800, 0x00CFFF },
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{ 0x00DD00, 0x00DDFF },
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{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
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{},
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};
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static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
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{ 0x00B000, 0x00B0FF },
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{ 0x00D800, 0x00D8FF },
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{},
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};
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static const struct intel_mmio_range dg2_lncf_steering_table[] = {
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{ 0x00B000, 0x00B0FF },
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{ 0x00D880, 0x00D8FF },
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{},
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};
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/*
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* We have several types of MCR registers on PVC where steering to (0,0)
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* will always provide us with a non-terminated value. We'll stick them
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* all in the same table for simplicity.
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*/
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static const struct intel_mmio_range pvc_instance0_steering_table[] = {
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{ 0x004000, 0x004AFF }, /* HALF-BSLICE */
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{ 0x008800, 0x00887F }, /* CC */
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{ 0x008A80, 0x008AFF }, /* TILEPSMI */
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{ 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
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{ 0x00B100, 0x00B3FF }, /* L3BANK */
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{ 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
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{ 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
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{ 0x00DD00, 0x00DDFF }, /* BSLICE */
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{ 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
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{ 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
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{ 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
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{ 0x024180, 0x0241FF }, /* HALF-BSLICE */
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{},
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};
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void intel_gt_mcr_init(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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/*
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* An mslice is unavailable only if both the meml3 for the slice is
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* disabled *and* all of the DSS in the slice (quadrant) are disabled.
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*/
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if (HAS_MSLICE_STEERING(i915)) {
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gt->info.mslice_mask =
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intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
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GEN_DSS_PER_MSLICE);
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gt->info.mslice_mask |=
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(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
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GEN12_MEML3_EN_MASK);
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if (!gt->info.mslice_mask) /* should be impossible! */
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drm_warn(&i915->drm, "mslice mask all zero!\n");
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}
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if (IS_PONTEVECCHIO(i915)) {
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gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
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} else if (IS_DG2(i915)) {
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gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
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gt->steering_table[LNCF] = dg2_lncf_steering_table;
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} else if (IS_XEHPSDV(i915)) {
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gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
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gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
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} else if (GRAPHICS_VER(i915) >= 11 &&
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GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
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gt->steering_table[L3BANK] = icl_l3bank_steering_table;
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gt->info.l3bank_mask =
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~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
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GEN10_L3BANK_MASK;
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if (!gt->info.l3bank_mask) /* should be impossible! */
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drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
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} else if (GRAPHICS_VER(i915) >= 11) {
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/*
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* We expect all modern platforms to have at least some
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* type of steering that needs to be initialized.
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*/
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MISSING_CASE(INTEL_INFO(i915)->platform);
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}
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}
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/*
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* rw_with_mcr_steering_fw - Access a register with specific MCR steering
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* @uncore: pointer to struct intel_uncore
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* @reg: register being accessed
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* @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access
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* @group: group number (documented as "sliceid" on older platforms)
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* @instance: instance number (documented as "subsliceid" on older platforms)
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* @value: register value to be written (ignored for read)
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*
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* Return: 0 for write access. register value for read access.
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*
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* Caller needs to make sure the relevant forcewake wells are up.
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*/
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static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
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i915_reg_t reg, u8 rw_flag,
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int group, int instance, u32 value)
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{
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u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
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lockdep_assert_held(&uncore->lock);
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if (GRAPHICS_VER(uncore->i915) >= 11) {
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mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
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mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance);
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/*
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* Wa_22013088509
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*
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* The setting of the multicast/unicast bit usually wouldn't
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* matter for read operations (which always return the value
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* from a single register instance regardless of how that bit
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* is set), but some platforms have a workaround requiring us
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* to remain in multicast mode for reads. There's no real
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* downside to this, so we'll just go ahead and do so on all
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* platforms; we'll only clear the multicast bit from the mask
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* when exlicitly doing a write operation.
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*/
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if (rw_flag == FW_REG_WRITE)
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mcr_mask |= GEN11_MCR_MULTICAST;
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} else {
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mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
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mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance);
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}
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old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
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mcr &= ~mcr_mask;
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mcr |= mcr_ss;
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
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if (rw_flag == FW_REG_READ)
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val = intel_uncore_read_fw(uncore, reg);
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else
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intel_uncore_write_fw(uncore, reg, value);
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mcr &= ~mcr_mask;
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mcr |= old_mcr & mcr_mask;
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intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
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return val;
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}
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static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
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i915_reg_t reg, u8 rw_flag,
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int group, int instance,
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u32 value)
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{
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enum forcewake_domains fw_domains;
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u32 val;
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fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
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rw_flag);
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fw_domains |= intel_uncore_forcewake_for_reg(uncore,
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GEN8_MCR_SELECTOR,
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FW_REG_READ | FW_REG_WRITE);
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spin_lock_irq(&uncore->lock);
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intel_uncore_forcewake_get__locked(uncore, fw_domains);
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val = rw_with_mcr_steering_fw(uncore, reg, rw_flag, group, instance, value);
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intel_uncore_forcewake_put__locked(uncore, fw_domains);
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spin_unlock_irq(&uncore->lock);
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return val;
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}
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/**
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* intel_gt_mcr_read - read a specific instance of an MCR register
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* @gt: GT structure
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* @reg: the MCR register to read
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* @group: the MCR group
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* @instance: the MCR instance
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*
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* Returns the value read from an MCR register after steering toward a specific
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* group/instance.
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*/
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u32 intel_gt_mcr_read(struct intel_gt *gt,
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i915_reg_t reg,
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int group, int instance)
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{
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return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group, instance, 0);
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}
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/**
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* intel_gt_mcr_unicast_write - write a specific instance of an MCR register
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* @gt: GT structure
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* @reg: the MCR register to write
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* @value: value to write
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* @group: the MCR group
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* @instance: the MCR instance
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*
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* Write an MCR register in unicast mode after steering toward a specific
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* group/instance.
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*/
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void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
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int group, int instance)
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{
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rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance, value);
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}
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/**
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* intel_gt_mcr_multicast_write - write a value to all instances of an MCR register
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* @gt: GT structure
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* @reg: the MCR register to write
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* @value: value to write
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*
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* Write an MCR register in multicast mode to update all instances.
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*/
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void intel_gt_mcr_multicast_write(struct intel_gt *gt,
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i915_reg_t reg, u32 value)
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{
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intel_uncore_write(gt->uncore, reg, value);
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}
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/**
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* intel_gt_mcr_multicast_write_fw - write a value to all instances of an MCR register
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* @gt: GT structure
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* @reg: the MCR register to write
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* @value: value to write
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*
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* Write an MCR register in multicast mode to update all instances. This
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* function assumes the caller is already holding any necessary forcewake
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* domains; use intel_gt_mcr_multicast_write() in cases where forcewake should
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* be obtained automatically.
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*/
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void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value)
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{
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intel_uncore_write_fw(gt->uncore, reg, value);
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}
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/*
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* reg_needs_read_steering - determine whether a register read requires
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* explicit steering
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* @gt: GT structure
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* @reg: the register to check steering requirements for
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* @type: type of multicast steering to check
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*
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* Determines whether @reg needs explicit steering of a specific type for
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* reads.
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*
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* Returns false if @reg does not belong to a register range of the given
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* steering type, or if the default (subslice-based) steering IDs are suitable
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* for @type steering too.
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*/
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static bool reg_needs_read_steering(struct intel_gt *gt,
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i915_reg_t reg,
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enum intel_steering_type type)
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{
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const u32 offset = i915_mmio_reg_offset(reg);
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const struct intel_mmio_range *entry;
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if (likely(!gt->steering_table[type]))
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return false;
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for (entry = gt->steering_table[type]; entry->end; entry++) {
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if (offset >= entry->start && offset <= entry->end)
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return true;
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}
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return false;
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}
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/*
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* get_nonterminated_steering - determines valid IDs for a class of MCR steering
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* @gt: GT structure
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* @type: multicast register type
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* @group: Group ID returned
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* @instance: Instance ID returned
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*
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* Determines group and instance values that will steer reads of the specified
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* MCR class to a non-terminated instance.
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*/
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static void get_nonterminated_steering(struct intel_gt *gt,
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enum intel_steering_type type,
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u8 *group, u8 *instance)
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{
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switch (type) {
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case L3BANK:
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*group = 0; /* unused */
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*instance = __ffs(gt->info.l3bank_mask);
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break;
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case MSLICE:
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GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
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*group = __ffs(gt->info.mslice_mask);
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*instance = 0; /* unused */
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break;
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case LNCF:
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/*
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* An LNCF is always present if its mslice is present, so we
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* can safely just steer to LNCF 0 in all cases.
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*/
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GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915));
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*group = __ffs(gt->info.mslice_mask) << 1;
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*instance = 0; /* unused */
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break;
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case INSTANCE0:
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/*
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* There are a lot of MCR types for which instance (0, 0)
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* will always provide a non-terminated value.
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*/
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*group = 0;
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*instance = 0;
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break;
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default:
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MISSING_CASE(type);
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*group = 0;
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*instance = 0;
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}
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}
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/**
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* intel_gt_mcr_get_nonterminated_steering - find group/instance values that
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* will steer a register to a non-terminated instance
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* @gt: GT structure
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* @reg: register for which the steering is required
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* @group: return variable for group steering
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* @instance: return variable for instance steering
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*
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* This function returns a group/instance pair that is guaranteed to work for
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* read steering of the given register. Note that a value will be returned even
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* if the register is not replicated and therefore does not actually require
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* steering.
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*/
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void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
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i915_reg_t reg,
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u8 *group, u8 *instance)
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{
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int type;
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for (type = 0; type < NUM_STEERING_TYPES; type++) {
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if (reg_needs_read_steering(gt, reg, type)) {
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get_nonterminated_steering(gt, type, group, instance);
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return;
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}
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}
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*group = gt->default_steering.groupid;
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*instance = gt->default_steering.instanceid;
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}
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/**
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* intel_gt_mcr_read_any_fw - reads one instance of an MCR register
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* @gt: GT structure
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* @reg: register to read
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*
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* Reads a GT MCR register. The read will be steered to a non-terminated
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* instance (i.e., one that isn't fused off or powered down by power gating).
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* This function assumes the caller is already holding any necessary forcewake
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* domains; use intel_gt_mcr_read_any() in cases where forcewake should be
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* obtained automatically.
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*
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* Returns the value from a non-terminated instance of @reg.
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*/
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u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
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{
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int type;
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u8 group, instance;
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for (type = 0; type < NUM_STEERING_TYPES; type++) {
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if (reg_needs_read_steering(gt, reg, type)) {
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get_nonterminated_steering(gt, type, &group, &instance);
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return rw_with_mcr_steering_fw(gt->uncore, reg,
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FW_REG_READ,
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group, instance, 0);
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}
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}
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return intel_uncore_read_fw(gt->uncore, reg);
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}
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/**
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* intel_gt_mcr_read_any - reads one instance of an MCR register
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* @gt: GT structure
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* @reg: register to read
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*
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* Reads a GT MCR register. The read will be steered to a non-terminated
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* instance (i.e., one that isn't fused off or powered down by power gating).
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*
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* Returns the value from a non-terminated instance of @reg.
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*/
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u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg)
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{
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int type;
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u8 group, instance;
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for (type = 0; type < NUM_STEERING_TYPES; type++) {
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if (reg_needs_read_steering(gt, reg, type)) {
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get_nonterminated_steering(gt, type, &group, &instance);
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return rw_with_mcr_steering(gt->uncore, reg,
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FW_REG_READ,
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group, instance, 0);
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}
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}
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return intel_uncore_read(gt->uncore, reg);
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}
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static void report_steering_type(struct drm_printer *p,
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struct intel_gt *gt,
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enum intel_steering_type type,
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bool dump_table)
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{
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const struct intel_mmio_range *entry;
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u8 group, instance;
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BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES);
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if (!gt->steering_table[type]) {
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drm_printf(p, "%s steering: uses default steering\n",
|
|
intel_steering_types[type]);
|
|
return;
|
|
}
|
|
|
|
get_nonterminated_steering(gt, type, &group, &instance);
|
|
drm_printf(p, "%s steering: group=0x%x, instance=0x%x\n",
|
|
intel_steering_types[type], group, instance);
|
|
|
|
if (!dump_table)
|
|
return;
|
|
|
|
for (entry = gt->steering_table[type]; entry->end; entry++)
|
|
drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end);
|
|
}
|
|
|
|
void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
|
|
bool dump_table)
|
|
{
|
|
drm_printf(p, "Default steering: group=0x%x, instance=0x%x\n",
|
|
gt->default_steering.groupid,
|
|
gt->default_steering.instanceid);
|
|
|
|
if (IS_PONTEVECCHIO(gt->i915)) {
|
|
report_steering_type(p, gt, INSTANCE0, dump_table);
|
|
} else if (HAS_MSLICE_STEERING(gt->i915)) {
|
|
report_steering_type(p, gt, MSLICE, dump_table);
|
|
report_steering_type(p, gt, LNCF, dump_table);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* intel_gt_mcr_get_ss_steering - returns the group/instance steering for a SS
|
|
* @gt: GT structure
|
|
* @dss: DSS ID to obtain steering for
|
|
* @group: pointer to storage for steering group ID
|
|
* @instance: pointer to storage for steering instance ID
|
|
*
|
|
* Returns the steering IDs (via the @group and @instance parameters) that
|
|
* correspond to a specific subslice/DSS ID.
|
|
*/
|
|
void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
|
|
unsigned int *group, unsigned int *instance)
|
|
{
|
|
if (IS_PONTEVECCHIO(gt->i915)) {
|
|
*group = dss / GEN_DSS_PER_CSLICE;
|
|
*instance = dss % GEN_DSS_PER_CSLICE;
|
|
} else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
|
|
*group = dss / GEN_DSS_PER_GSLICE;
|
|
*instance = dss % GEN_DSS_PER_GSLICE;
|
|
} else {
|
|
*group = dss / GEN_MAX_SS_PER_HSW_SLICE;
|
|
*instance = dss % GEN_MAX_SS_PER_HSW_SLICE;
|
|
return;
|
|
}
|
|
}
|