520 lines
15 KiB
C
520 lines
15 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/sched/clock.h>
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#include "i915_drv.h"
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#include "i915_irq.h"
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#include "intel_breadcrumbs.h"
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#include "intel_gt.h"
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#include "intel_gt_irq.h"
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#include "intel_gt_regs.h"
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#include "intel_uncore.h"
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#include "intel_rps.h"
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#include "pxp/intel_pxp_irq.h"
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static void guc_irq_handler(struct intel_guc *guc, u16 iir)
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{
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if (iir & GUC_INTR_GUC2HOST)
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intel_guc_to_host_event_handler(guc);
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}
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static u32
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gen11_gt_engine_identity(struct intel_gt *gt,
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const unsigned int bank, const unsigned int bit)
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{
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void __iomem * const regs = gt->uncore->regs;
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u32 timeout_ts;
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u32 ident;
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lockdep_assert_held(gt->irq_lock);
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raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
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/*
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* NB: Specs do not specify how long to spin wait,
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* so we do ~100us as an educated guess.
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*/
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timeout_ts = (local_clock() >> 10) + 100;
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do {
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ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
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} while (!(ident & GEN11_INTR_DATA_VALID) &&
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!time_after32(local_clock() >> 10, timeout_ts));
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if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
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DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
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bank, bit, ident);
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return 0;
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}
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raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
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GEN11_INTR_DATA_VALID);
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return ident;
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}
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static void
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gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
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const u16 iir)
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{
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struct intel_gt *media_gt = gt->i915->media_gt;
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if (instance == OTHER_GUC_INSTANCE)
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return guc_irq_handler(>->uc.guc, iir);
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if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
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return guc_irq_handler(&media_gt->uc.guc, iir);
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if (instance == OTHER_GTPM_INSTANCE)
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return gen11_rps_irq_handler(>->rps, iir);
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if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
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return gen11_rps_irq_handler(&media_gt->rps, iir);
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if (instance == OTHER_KCR_INSTANCE)
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return intel_pxp_irq_handler(>->pxp, iir);
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if (instance == OTHER_GSC_INSTANCE)
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return intel_gsc_irq_handler(gt, iir);
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WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
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instance, iir);
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}
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static void
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gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
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const u8 instance, const u16 iir)
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{
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struct intel_engine_cs *engine;
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/*
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* Platforms with standalone media have their media engines in another
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* GT.
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*/
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if (MEDIA_VER(gt->i915) >= 13 &&
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(class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
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if (!gt->i915->media_gt)
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goto err;
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gt = gt->i915->media_gt;
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}
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if (instance <= MAX_ENGINE_INSTANCE)
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engine = gt->engine_class[class][instance];
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else
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engine = NULL;
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if (likely(engine))
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return intel_engine_cs_irq(engine, iir);
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err:
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WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
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class, instance);
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}
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static void
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gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
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{
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const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
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const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
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const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
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if (unlikely(!intr))
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return;
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if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
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return gen11_engine_irq_handler(gt, class, instance, intr);
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if (class == OTHER_CLASS)
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return gen11_other_irq_handler(gt, instance, intr);
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WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
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class, instance, intr);
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}
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static void
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gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
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{
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void __iomem * const regs = gt->uncore->regs;
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unsigned long intr_dw;
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unsigned int bit;
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lockdep_assert_held(gt->irq_lock);
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intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
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for_each_set_bit(bit, &intr_dw, 32) {
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const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
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gen11_gt_identity_handler(gt, ident);
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}
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/* Clear must be after shared has been served for engine */
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raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
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}
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void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
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{
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unsigned int bank;
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spin_lock(gt->irq_lock);
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for (bank = 0; bank < 2; bank++) {
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if (master_ctl & GEN11_GT_DW_IRQ(bank))
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gen11_gt_bank_handler(gt, bank);
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}
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spin_unlock(gt->irq_lock);
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}
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bool gen11_gt_reset_one_iir(struct intel_gt *gt,
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const unsigned int bank, const unsigned int bit)
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{
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void __iomem * const regs = gt->uncore->regs;
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u32 dw;
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lockdep_assert_held(gt->irq_lock);
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dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
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if (dw & BIT(bit)) {
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/*
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* According to the BSpec, DW_IIR bits cannot be cleared without
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* first servicing the Selector & Shared IIR registers.
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*/
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gen11_gt_engine_identity(gt, bank, bit);
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/*
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* We locked GT INT DW by reading it. If we want to (try
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* to) recover from this successfully, we need to clear
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* our bit, otherwise we are locking the register for
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* everybody.
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*/
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raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
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return true;
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}
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return false;
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}
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void gen11_gt_irq_reset(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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/* Disable RCS, BCS, VCS and VECS class engines. */
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intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
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intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
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if (CCS_MASK(gt))
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intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
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if (HAS_HECI_GSC(gt->i915))
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intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
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/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
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intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
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intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
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intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
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intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
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intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
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intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
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intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
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intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
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intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
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if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
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intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
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if (HAS_HECI_GSC(gt->i915))
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intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
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intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
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intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
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intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
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intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
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}
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void gen11_gt_irq_postinstall(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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u32 irqs = GT_RENDER_USER_INTERRUPT;
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const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
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u32 dmask;
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u32 smask;
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if (!intel_uc_wants_guc_submission(>->uc))
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irqs |= GT_CS_MASTER_ERROR_INTERRUPT |
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GT_CONTEXT_SWITCH_INTERRUPT |
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GT_WAIT_SEMAPHORE_INTERRUPT;
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dmask = irqs << 16 | irqs;
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smask = irqs << 16;
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BUILD_BUG_ON(irqs & 0xffff0000);
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/* Enable RCS, BCS, VCS and VECS class interrupts. */
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intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
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intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
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if (CCS_MASK(gt))
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intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
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if (HAS_HECI_GSC(gt->i915))
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intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
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gsc_mask);
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/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
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intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
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intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
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if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
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intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
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intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
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intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
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intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
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intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
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intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
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intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
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intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
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intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
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intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
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intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
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if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
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intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
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if (HAS_HECI_GSC(gt->i915))
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intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
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/*
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* RPS interrupts will get enabled/disabled on demand when RPS itself
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* is enabled/disabled.
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*/
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gt->pm_ier = 0x0;
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gt->pm_imr = ~gt->pm_ier;
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intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
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intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
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/* Same thing for GuC interrupts */
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intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
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intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
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}
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void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
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{
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if (gt_iir & GT_RENDER_USER_INTERRUPT)
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intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
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gt_iir);
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if (gt_iir & ILK_BSD_USER_INTERRUPT)
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intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
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gt_iir);
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}
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static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
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{
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if (!HAS_L3_DPF(gt->i915))
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return;
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spin_lock(gt->irq_lock);
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gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));
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spin_unlock(gt->irq_lock);
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if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
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gt->i915->l3_parity.which_slice |= 1 << 1;
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if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
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gt->i915->l3_parity.which_slice |= 1 << 0;
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schedule_work(>->i915->l3_parity.error_work);
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}
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void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
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{
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if (gt_iir & GT_RENDER_USER_INTERRUPT)
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intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
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gt_iir);
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if (gt_iir & GT_BSD_USER_INTERRUPT)
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intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
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gt_iir >> 12);
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if (gt_iir & GT_BLT_USER_INTERRUPT)
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intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
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gt_iir >> 22);
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if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
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GT_BSD_CS_ERROR_INTERRUPT |
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GT_CS_MASTER_ERROR_INTERRUPT))
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DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
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if (gt_iir & GT_PARITY_ERROR(gt->i915))
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gen7_parity_error_irq_handler(gt, gt_iir);
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}
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void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
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{
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void __iomem * const regs = gt->uncore->regs;
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u32 iir;
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if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
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iir = raw_reg_read(regs, GEN8_GT_IIR(0));
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if (likely(iir)) {
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intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],
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iir >> GEN8_RCS_IRQ_SHIFT);
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intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],
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iir >> GEN8_BCS_IRQ_SHIFT);
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raw_reg_write(regs, GEN8_GT_IIR(0), iir);
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}
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}
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if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
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iir = raw_reg_read(regs, GEN8_GT_IIR(1));
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if (likely(iir)) {
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intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],
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iir >> GEN8_VCS0_IRQ_SHIFT);
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intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1],
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iir >> GEN8_VCS1_IRQ_SHIFT);
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raw_reg_write(regs, GEN8_GT_IIR(1), iir);
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}
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}
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if (master_ctl & GEN8_GT_VECS_IRQ) {
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iir = raw_reg_read(regs, GEN8_GT_IIR(3));
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if (likely(iir)) {
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intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
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iir >> GEN8_VECS_IRQ_SHIFT);
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raw_reg_write(regs, GEN8_GT_IIR(3), iir);
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}
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}
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if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
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iir = raw_reg_read(regs, GEN8_GT_IIR(2));
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if (likely(iir)) {
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gen6_rps_irq_handler(>->rps, iir);
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guc_irq_handler(>->uc.guc, iir >> 16);
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raw_reg_write(regs, GEN8_GT_IIR(2), iir);
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}
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}
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}
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void gen8_gt_irq_reset(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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GEN8_IRQ_RESET_NDX(uncore, GT, 0);
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GEN8_IRQ_RESET_NDX(uncore, GT, 1);
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GEN8_IRQ_RESET_NDX(uncore, GT, 2);
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GEN8_IRQ_RESET_NDX(uncore, GT, 3);
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}
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void gen8_gt_irq_postinstall(struct intel_gt *gt)
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{
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/* These are interrupts we'll toggle with the ring mask register */
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const u32 irqs =
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GT_CS_MASTER_ERROR_INTERRUPT |
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GT_RENDER_USER_INTERRUPT |
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GT_CONTEXT_SWITCH_INTERRUPT |
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GT_WAIT_SEMAPHORE_INTERRUPT;
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const u32 gt_interrupts[] = {
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irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
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irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
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0,
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irqs << GEN8_VECS_IRQ_SHIFT,
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};
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struct intel_uncore *uncore = gt->uncore;
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|
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gt->pm_ier = 0x0;
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gt->pm_imr = ~gt->pm_ier;
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GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
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GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
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/*
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* RPS interrupts will get enabled/disabled on demand when RPS itself
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* is enabled/disabled. Same wil be the case for GuC interrupts.
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*/
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GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);
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GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
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}
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static void gen5_gt_update_irq(struct intel_gt *gt,
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u32 interrupt_mask,
|
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u32 enabled_irq_mask)
|
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{
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lockdep_assert_held(gt->irq_lock);
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|
|
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GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask);
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|
|
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gt->gt_imr &= ~interrupt_mask;
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|
gt->gt_imr |= (~enabled_irq_mask & interrupt_mask);
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intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr);
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}
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void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask)
|
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{
|
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gen5_gt_update_irq(gt, mask, mask);
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intel_uncore_posting_read_fw(gt->uncore, GTIMR);
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}
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|
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void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask)
|
|
{
|
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gen5_gt_update_irq(gt, mask, 0);
|
|
}
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|
|
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void gen5_gt_irq_reset(struct intel_gt *gt)
|
|
{
|
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struct intel_uncore *uncore = gt->uncore;
|
|
|
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GEN3_IRQ_RESET(uncore, GT);
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if (GRAPHICS_VER(gt->i915) >= 6)
|
|
GEN3_IRQ_RESET(uncore, GEN6_PM);
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}
|
|
|
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void gen5_gt_irq_postinstall(struct intel_gt *gt)
|
|
{
|
|
struct intel_uncore *uncore = gt->uncore;
|
|
u32 pm_irqs = 0;
|
|
u32 gt_irqs = 0;
|
|
|
|
gt->gt_imr = ~0;
|
|
if (HAS_L3_DPF(gt->i915)) {
|
|
/* L3 parity interrupt is always unmasked. */
|
|
gt->gt_imr = ~GT_PARITY_ERROR(gt->i915);
|
|
gt_irqs |= GT_PARITY_ERROR(gt->i915);
|
|
}
|
|
|
|
gt_irqs |= GT_RENDER_USER_INTERRUPT;
|
|
if (GRAPHICS_VER(gt->i915) == 5)
|
|
gt_irqs |= ILK_BSD_USER_INTERRUPT;
|
|
else
|
|
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
|
|
|
|
GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
|
|
|
|
if (GRAPHICS_VER(gt->i915) >= 6) {
|
|
/*
|
|
* RPS interrupts will get enabled/disabled on demand when RPS
|
|
* itself is enabled/disabled.
|
|
*/
|
|
if (HAS_ENGINE(gt, VECS0)) {
|
|
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
|
|
gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;
|
|
}
|
|
|
|
gt->pm_imr = 0xffffffff;
|
|
GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs);
|
|
}
|
|
}
|