194 lines
6.6 KiB
C
194 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Renesas Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2015 Glider bvba
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*/
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#ifndef __CLK_RENESAS_CPG_MSSR_H__
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#define __CLK_RENESAS_CPG_MSSR_H__
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/*
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* Definitions of CPG Core Clocks
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*
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* These include:
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* - Clock outputs exported to DT
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* - External input clocks
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* - Internal CPG clocks
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*/
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struct cpg_core_clk {
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/* Common */
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const char *name;
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unsigned int id;
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unsigned int type;
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/* Depending on type */
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unsigned int parent; /* Core Clocks only */
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unsigned int div;
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unsigned int mult;
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unsigned int offset;
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};
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enum clk_types {
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/* Generic */
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CLK_TYPE_IN, /* External Clock Input */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
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CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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CLK_TYPE_FR, /* Fixed Rate Clock */
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/* Custom definitions start here */
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CLK_TYPE_CUSTOM,
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};
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#define DEF_TYPE(_name, _id, _type...) \
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{ .name = _name, .id = _id, .type = _type }
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#define DEF_BASE(_name, _id, _type, _parent...) \
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DEF_TYPE(_name, _id, _type, .parent = _parent)
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#define DEF_INPUT(_name, _id) \
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DEF_TYPE(_name, _id, CLK_TYPE_IN)
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#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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#define DEF_DIV6P1(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
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#define DEF_RATE(_name, _id, _rate) \
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DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
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/*
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* Definitions of Module Clocks
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*/
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struct mssr_mod_clk {
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const char *name;
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unsigned int id;
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unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
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};
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/* Convert from sparse base-100 to packed index space */
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#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
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#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
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#define DEF_MOD(_name, _mod, _parent...) \
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{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
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/* Convert from sparse base-10 to packed index space */
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#define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))
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#define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
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#define DEF_MOD_STB(_name, _mod, _parent...) \
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{ .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
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struct device_node;
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enum clk_reg_layout {
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CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
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CLK_REG_LAYOUT_RZ_A,
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CLK_REG_LAYOUT_RCAR_GEN4,
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};
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/**
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* SoC-specific CPG/MSSR Description
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*
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* @early_core_clks: Array of Early Core Clock definitions
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* @num_early_core_clks: Number of entries in early_core_clks[]
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* @early_mod_clks: Array of Early Module Clock definitions
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* @num_early_mod_clks: Number of entries in early_mod_clks[]
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*
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* @core_clks: Array of Core Clock definitions
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* @num_core_clks: Number of entries in core_clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @num_total_core_clks: Total number of Core Clocks (exported + internal)
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*
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* @mod_clks: Array of Module Clock definitions
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* @num_mod_clks: Number of entries in mod_clks[]
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* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
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*
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* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
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* should not be disabled without a knowledgeable driver
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* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
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* @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
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*
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* @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
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* Management, in addition to Module Clocks
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* @num_core_pm_clks: Number of entries in core_pm_clks[]
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*
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* @init: Optional callback to perform SoC-specific initialization
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* @cpg_clk_register: Optional callback to handle special Core Clock types
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*/
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struct cpg_mssr_info {
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/* Early Clocks */
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const struct cpg_core_clk *early_core_clks;
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unsigned int num_early_core_clks;
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const struct mssr_mod_clk *early_mod_clks;
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unsigned int num_early_mod_clks;
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/* Core Clocks */
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const struct cpg_core_clk *core_clks;
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unsigned int num_core_clks;
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unsigned int last_dt_core_clk;
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unsigned int num_total_core_clks;
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enum clk_reg_layout reg_layout;
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/* Module Clocks */
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const struct mssr_mod_clk *mod_clks;
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unsigned int num_mod_clks;
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unsigned int num_hw_mod_clks;
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/* Critical Module Clocks that should not be disabled */
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const unsigned int *crit_mod_clks;
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unsigned int num_crit_mod_clks;
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/* Core Clocks suitable for PM, in addition to the Module Clocks */
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const unsigned int *core_pm_clks;
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unsigned int num_core_pm_clks;
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/* Callbacks */
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int (*init)(struct device *dev);
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struct clk *(*cpg_clk_register)(struct device *dev,
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const struct cpg_core_clk *core,
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const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers);
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};
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extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
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extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
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void __init cpg_mssr_early_init(struct device_node *np,
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const struct cpg_mssr_info *info);
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/*
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* Helpers for fixing up clock tables depending on SoC revision
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*/
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extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
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unsigned int num_mod_clks,
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const unsigned int *clks, unsigned int n);
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#endif
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