358 lines
7.2 KiB
Plaintext
358 lines
7.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
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*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <dt-bindings/clock/oxsemi,ox810se.h>
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#include <dt-bindings/reset/oxsemi,ox810se.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "oxsemi,ox810se";
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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clocks = <&armclk>;
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};
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};
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memory {
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device_type = "memory";
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/* Max 256MB @ 0x48000000 */
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reg = <0x48000000 0x10000000>;
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};
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clocks {
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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gmacclk: gmacclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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rpsclk: rpsclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&osc>;
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};
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pll400: pll400 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <733333333>;
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};
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sysclk: sysclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll400>;
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};
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armclk: armclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll400>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&intc>;
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etha: ethernet@40400000 {
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compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
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reg = <0x40400000 0x2000>;
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interrupts = <8>;
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interrupt-names = "macirq";
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mac-address = [000000000000]; /* Filled in by U-Boot */
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phy-mode = "rgmii";
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clocks = <&stdclk 6>, <&gmacclk>;
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clock-names = "gmac", "stmmaceth";
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resets = <&reset 6>;
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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status = "disabled";
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};
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apb-bridge@44000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x44000000 0x1000000>;
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pinctrl: pinctrl {
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compatible = "oxsemi,ox810se-pinctrl";
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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pinctrl_uart0: uart0 {
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uart0a {
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pins = "gpio31";
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function = "fct3";
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};
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uart0b {
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pins = "gpio32";
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function = "fct3";
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};
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};
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pinctrl_uart0_modem: uart0_modem {
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uart0c {
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pins = "gpio27";
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function = "fct3";
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};
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uart0d {
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pins = "gpio28";
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function = "fct3";
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};
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uart0e {
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pins = "gpio29";
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function = "fct3";
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};
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uart0f {
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pins = "gpio30";
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function = "fct3";
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};
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uart0g {
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pins = "gpio33";
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function = "fct3";
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};
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uart0h {
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pins = "gpio34";
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function = "fct3";
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};
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};
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pinctrl_uart1: uart1 {
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uart1a {
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pins = "gpio20";
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function = "fct3";
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};
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uart1b {
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pins = "gpio22";
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function = "fct3";
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};
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};
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pinctrl_uart1_modem: uart1_modem {
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uart1c {
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pins = "gpio8";
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function = "fct3";
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};
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uart1d {
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pins = "gpio9";
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function = "fct3";
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};
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uart1e {
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pins = "gpio23";
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function = "fct3";
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};
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uart1f {
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pins = "gpio24";
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function = "fct3";
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};
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uart1g {
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pins = "gpio25";
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function = "fct3";
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};
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uart1h {
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pins = "gpio26";
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function = "fct3";
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};
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};
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pinctrl_uart2: uart2 {
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uart2a {
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pins = "gpio6";
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function = "fct3";
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};
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uart2b {
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pins = "gpio7";
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function = "fct3";
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};
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};
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pinctrl_uart2_modem: uart2_modem {
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uart2c {
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pins = "gpio0";
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function = "fct3";
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};
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uart2d {
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pins = "gpio1";
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function = "fct3";
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};
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uart2e {
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pins = "gpio2";
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function = "fct3";
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};
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uart2f {
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pins = "gpio3";
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function = "fct3";
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};
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uart2g {
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pins = "gpio4";
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function = "fct3";
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};
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uart2h {
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pins = "gpio5";
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function = "fct3";
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};
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};
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};
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gpio0: gpio@0 {
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compatible = "oxsemi,ox810se-gpio";
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reg = <0x000000 0x100000>;
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interrupts = <21>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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ngpios = <32>;
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oxsemi,gpio-bank = <0>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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gpio1: gpio@100000 {
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compatible = "oxsemi,ox810se-gpio";
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reg = <0x100000 0x100000>;
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interrupts = <22>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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ngpios = <3>;
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oxsemi,gpio-bank = <1>;
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gpio-ranges = <&pinctrl 0 32 3>;
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};
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uart0: serial@200000 {
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compatible = "ns16550a";
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reg = <0x200000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <23>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART1>;
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};
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uart1: serial@300000 {
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compatible = "ns16550a";
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reg = <0x300000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <24>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART2>;
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};
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uart2: serial@900000 {
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compatible = "ns16550a";
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reg = <0x900000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <29>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART3>;
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};
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uart3: serial@a00000 {
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compatible = "ns16550a";
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reg = <0xa00000 0x100000>;
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clocks = <&sysclk>;
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interrupts = <30>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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resets = <&reset RESET_UART4>;
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};
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};
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apb-bridge@45000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x45000000 0x1000000>;
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sys: sys-ctrl@0 {
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compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
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reg = <0x000000 0x100000>;
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reset: reset-controller {
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compatible = "oxsemi,ox810se-reset";
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#reset-cells = <1>;
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};
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stdclk: stdclk {
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compatible = "oxsemi,ox810se-stdclk";
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#clock-cells = <1>;
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};
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};
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rps@300000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x300000 0x100000>;
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intc: interrupt-controller@0 {
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compatible = "oxsemi,ox810se-rps-irq";
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interrupt-controller;
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reg = <0 0x200>;
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#interrupt-cells = <1>;
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valid-mask = <0xffffffff>;
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clear-mask = <0xffffffff>;
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};
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timer0: timer@200 {
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compatible = "oxsemi,ox810se-rps-timer";
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reg = <0x200 0x40>;
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clocks = <&rpsclk>;
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interrupts = <4 5>;
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};
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};
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};
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};
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};
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