linuxdebug/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml

103 lines
2.5 KiB
YAML

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5P/Exynos SoC USB 2.0 PHY
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Marek Szyprowski <m.szyprowski@samsung.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
description: |
The first phandle argument in the PHY specifier identifies the PHY, its
meaning is compatible dependent. For the currently supported SoCs (Exynos4210
and Exynos4212) it is as follows::
0 - USB device ("device"),
1 - USB host ("host"),
2 - HSIC0 ("hsic0"),
3 - HSIC1 ("hsic1"),
Exynos3250 has only USB device phy available as phy 0.
Exynos4210 and Exynos4212 use mode switching and require that mode switch
register is supplied.
properties:
compatible:
enum:
- samsung,exynos3250-usb2-phy
- samsung,exynos4210-usb2-phy
- samsung,exynos4x12-usb2-phy
- samsung,exynos5250-usb2-phy
- samsung,exynos5420-usb2-phy
- samsung,s5pv210-usb2-phy
clocks:
items:
- description: PHY module gate clock.
- description: Reference rate clock of PHY module.
clock-names:
items:
- const: phy
- const: ref
"#phy-cells":
const: 1
reg:
maxItems: 1
samsung,pmureg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface.
samsung,sysreg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to system registers interface.
vbus-supply:
description:
VBUS power source.
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
- reg
- samsung,pmureg-phandle
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos4x12-usb2-phy
- samsung,exynos5250-usb2-phy
- samsung,exynos5420-usb2-phy
then:
required:
- samsung,sysreg-phandle
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
phy@12130000 {
compatible = "samsung,exynos5420-usb2-phy";
reg = <0x12130000 0x100>;
#phy-cells = <1>;
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};