178 lines
6.1 KiB
YAML
178 lines
6.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic PCI host controller
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maintainers:
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- Will Deacon <will@kernel.org>
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description: |
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Firmware-initialised PCI host controllers and PCI emulations, such as the
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virtio-pci implementations found in kvmtool and other para-virtualised
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systems, do not require driver support for complexities such as regulator
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and clock management. In fact, the controller may not even require the
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configuration of a control interface by the operating system, instead
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presenting a set of fixed windows describing a subset of IO, Memory and
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Configuration Spaces.
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Configuration Space is assumed to be memory-mapped (as opposed to being
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accessed via an ioport) and laid out with a direct correspondence to the
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geography of a PCI bus address by concatenating the various components to
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form an offset.
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For CAM, this 24-bit offset is:
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cfg_offset(bus, device, function, register) =
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bus << 16 | device << 11 | function << 8 | register
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While ECAM extends this by 4 bits to accommodate 4k of function space:
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cfg_offset(bus, device, function, register) =
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bus << 20 | device << 15 | function << 12 | register
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properties:
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compatible:
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description: Depends on the layout of configuration space (CAM vs ECAM
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respectively). May also have more specific compatibles.
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oneOf:
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- description:
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PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
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items:
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- const: arm,juno-r1-pcie
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- const: plda,xpressrich3-axi
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- const: pci-host-ecam-generic
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- description: |
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ThunderX PCI host controller for pass-1.x silicon
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Firmware-initialized PCI host controller to on-chip devices found on
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some Cavium ThunderX processors. These devices have ECAM-based config
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access, but the BARs are all at fixed addresses. We handle the fixed
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addresses by synthesizing Enhanced Allocation (EA) capabilities for
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these devices.
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const: cavium,pci-host-thunder-ecam
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- description:
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Cavium ThunderX PEM firmware-initialized PCIe host controller
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const: cavium,pci-host-thunder-pem
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- description:
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HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
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firmware places the host controller in a mode where it is ECAM
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compliant for all devices other than the root complex.
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enum:
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- hisilicon,hip06-pcie-ecam
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- hisilicon,hip07-pcie-ecam
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- description: |
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In some cases, firmware may already have configured the Synopsys
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DesignWare PCIe controller in RC mode with static ATU window mappings
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that cover all config, MMIO and I/O spaces in a [mostly] ECAM
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compatible fashion. In this case, there is no need for the OS to
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perform any low level setup of clocks, PHYs or device registers, nor
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is there any reason for the driver to reconfigure ATU windows for
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config and/or IO space accesses at runtime.
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In cases where the IP was synthesized with a minimum ATU window size
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of 64 KB, it cannot be supported by the generic ECAM driver, because
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it requires special config space accessors that filter accesses to
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device #1 and beyond on the first bus.
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items:
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- enum:
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- marvell,armada8k-pcie-ecam
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- socionext,synquacer-pcie-ecam
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- const: snps,dw-pcie-ecam
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- description:
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CAM or ECAM compliant PCI host controllers without any quirks
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enum:
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- pci-host-cam-generic
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- pci-host-ecam-generic
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reg:
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description:
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The Configuration Space base address and size, as accessed from the parent
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bus. The base address corresponds to the first bus in the "bus-range"
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property. If no "bus-range" is specified, this will be bus 0 (the
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default). Some host controllers have a 2nd non-compliant address range,
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so 2 entries are allowed.
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minItems: 1
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maxItems: 2
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ranges:
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description:
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As described in IEEE Std 1275-1994, but must provide at least a
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definition of non-prefetchable memory. One or both of prefetchable Memory
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and IO Space may also be provided.
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minItems: 1
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maxItems: 3
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dma-coherent: true
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iommu-map: true
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iommu-map-mask: true
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msi-parent: true
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required:
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- compatible
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- reg
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- ranges
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: arm,juno-r1-pcie
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then:
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required:
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- dma-coherent
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- if:
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properties:
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compatible:
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not:
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contains:
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enum:
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- cavium,pci-host-thunder-pem
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- hisilicon,hip06-pcie-ecam
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- hisilicon,hip07-pcie-ecam
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then:
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properties:
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reg:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@40000000 {
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compatible = "pci-host-cam-generic";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0x1>;
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// CPU_PHYSICAL(2) SIZE(2)
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reg = <0x0 0x40000000 0x0 0x1000000>;
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// BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
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ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
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<0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
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#interrupt-cells = <0x1>;
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// PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3)
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interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
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< 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
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<0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
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<0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
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// PCI_DEVICE(3) INT#(1)
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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};
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};
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...
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